Abstract: A method for forming a MOSFET includes the steps of forming cobalt silicide layers on a polysilicon gate electrode and source/drain regions, implanting impurity ions to form source/drain extensions and diffusing the impurity ions in the source/drain extensions The temperature of the heat treatment for diffusing step is lower than the maximum of the temperatures of the heat treatment for forming the silicide layer, whereby a MOSFET having excellent short-channel characteristics and a higher reliability can be obtained.

Abstract: A core section complementary transistor and a memory cell section complementary transistor are formed on a semiconductor substrate of a first conductivity type. The core section complementary transistor has a first well of a second conductivity type provided in the semiconductor substrate, a first core section MOS transistor provided on the first well of the second conductivity type, a second core section MOS transistor provided on the semiconductor substrate a device separation film which separates the first core section MOS transistor and the second core section MOS transistor from each other, and a well of the first conductivity type provided under a part of the device separation film which is closer to the second core section MOS transistor. The first core section MOS transistor has source-drain regions of the first conductivity type. The second core section MOS transistor has source-drain regions of the second conductivity type.

Abstract: A method for forming a semiconductor device that has a fully depleted MOSFET and a partially depleted MOSFET having excellent characteristics on the same substrate without effecting control by means of the impurity concentration of the channel region. A semiconductor device is provided with a fully-depleted SOI MOSFET and a partially-depleted SOI MOSFET on the same SOI substrate through isolation by an element isolation film. The SOI substrate includes a buried oxide film and a SOI layer provided in succession on a silicon substrate.

Abstract: In an integrated circuit device, third transistors having the thickest gate insulation film are driven at high voltage and thus operate at high speed with minimal gate leak current. First transistors having the thinnest gate insulation film and second transistors which do not have the thinnest gate insulation film are driven at low voltage, the second transistors being driven at all times and the first transistors being halted as appropriate. The second transistors operate constantly at low speed and with minimal gate leak current, and the first transistors, which have significant gate leak current, operate at high speed while halting as appropriate.

Abstract: In an integrated circuit device, third transistors having the thickest gate insulation film are driven at high voltage and thus operate at high speed with minimal gate leak current. First transistors having the thinnest gate insulation film and second transistors which do not have the thinnest gate insulation film are driven at low voltage, the second transistors being driven at all times and the first transistors being halted as appropriate. The second transistors operate constantly at low speed and with minimal gate leak current, and the first transistors, which have significant gate leak current, operate at high speed while halting as appropriate.

Abstract: A semiconductor device including an NMOSFET which has an n-type source/drain main region containing arsenic and an n-type source/drain buffer region having arsenic and phosphorous of which a concentration is lower than that of the source/drain main region, and the concentration of the phosphorous in the source/drain buffer region is smaller than the concentration of the arsenic therein. The semiconductor device has a suppressed reverse short channel effect and reduced p-n junction leakage current. Further, the semiconductor device has a larger margin to a certain gate length and a specified threshold voltage to elevate a production yield.

Abstract: There is provided a reticle used for fabrication of a semiconductor device, including (a) a first area in which a first mask having a first pattern is formed for forming a first contact hole having a first size, and (b) a second area in which a second mask having a second pattern is formed for forming a second contact hole having a second size different from the first size. The reticle makes it possible to transfer a contact pattern to a resist film in exposure conditions suitable for a size of a contact hole. Thus, a contact hole is transferred to a resist film in a designed dimension regardless of a size thereof.

Abstract: In a method of manufacturing a semiconductor device having first through third MOS transistors, using a first mask (311), wells (313, 314) and first threshold adjustment regions (315, 316) are formed at transistor areas (306n, 308n) for the second and the third MOS transistors in a semiconductor substrate (301). Next, using a second mask (319), second threshold adjustment regions (320, 321) are formed at transistor areas (304n and 308n) for the first and the third MOS transistors. In the transistor area for the third MOS transistor, both of the first threshold adjustment region and the second threshold adjustment region form a third adjustment region. Thus, using the two masks, three thresholds of the MOS transistors are obtained.

Abstract: The present invention provides a source/drain structure formed in a semiconductor layer which has source and drain regions of a first conductivity type and a body portion of a second conductivity type disposed between said source and drain regions. The body portion is positioned under a gate insulation film over which a gate electrode is provided. The source region has a first low resistive region which is lower in electrical resistivity than said source region and said drain region having a second low resistive region which is lower in electrical resistively than said source region. For the first present invention, it is important that a distance of an inside edge portion of the first low resistive region from a first interface between the source region and the body portion is shorter than a distance of an inside portion of the second low resistive region from a second interface between the drain region and the body portion.

Abstract: In a semiconductor device having a multilayer metallization structure using SiOF film as an interlayer insulating film, with respect to the interlayer insulating film, the fluorine concentration of SiOF films (11, 16) in a wiring gap portion in the same layer wiring is set to be higher than the fluorine concentration of SiOF films (12, 17) between the upper and lower layer wirings (8, 15; 15, 20).

Abstract: In a method of manufacturing a semiconductor device having first through third MOS transistors, using a first mask (311), wells (313, 314) and first threshold adjustment regions (315, 316) are formed at transistor areas (306n, 308n) for the second and the third MOS transistors in a semiconductor substrate (301). Next, using a second mask (319), second threshold adjustment regions (320, 321) are formed at transistor areas (304n and 308n) for the first and the third MOS transistors. In the transistor area for the third MOS transistor, both of the first threshold adjustment region and the second threshold adjustment region form a third adjustment region. Thus, using the two masks, three thresholds of the MOS transistors are obtained.

Abstract: Manufactured is a semiconductor device that has a substrate and a surface channel nMOS and a buried channel nMOS as well as a surface channel pMOS and a buried channel pMOS formed on the substrate. An n+ dopant is introduced prior to pattering a polycrystalline semiconductor layer that forms respective gate electrodes of the surface channel nMOS and the buried channel pMOS. A p+ dopant is also introduced prior to pattering a polycrystalline semiconductor layer that forms respective gate electrodes of the surface channel pMOS and the buried channel nMOS.

Abstract: A semiconductor device is provided which is capable of suppressing an increase in the layer resistance of the gate electrode and preventing an increase of the contact resistance of the gate electrode with the silicide layer. The above properties of the semiconductor device are provided by forming the gate electrode comprising multiple layers, and the lowermost layer of the gate electrode is doped with an impurity, and other upper layers are formed undoped.

Abstract: In a semiconductor device having a multilayer metallization structure using SiOF film as an interlayer insulating film, with respect to the interlayer insulating film, the fluorine concentration of SiOF films (11, 16) in a wiring gap portion in the same layer wiring is set to be higher than the fluorine concentration of SiOF films (12, 17) between the upper and lower layer wirings (8, 15; 15, 20).

Abstract: The invention provides a semiconductor device that has a fully depleted MOSFET and a partially depleted MOSFET having excellent characteristics on the same substrate without effecting control by means of the impurity concentration of the channel region. In FIG. 2E, semiconductor device 10 is provided with fully-depleted SOI MOSFET 12 and partially-depleted SOI MOSFET 14 on the same SOI substrate through isolation by element isolation film 4. SOI substrate includes buried oxide film 2 and SOI layer 3 provided in succession on silicon substrate 1. Film thickness TOX1 of gate oxide film 5 is 8 nm, film thickness TSOI1 of SOI layer 3 is 56 nm, and boron concentration NA1 of the channel region is 3×1017cm−3 in fully-depleted SOI MOSFET 12. In contrast, film thickness TOX2 of gate oxide film 5 is 12 nm, film thickness TSOI2 of SOI layer 3 is 59 nm, and boron concentration NA2 of the channel region is 5×1017cm−3 in partially-depleted SOI MOSFET 14.

Abstract: The invention provides a semiconductor device that has a fully depleted MOSFET and a partially depleted MOSFET having excellent characteristics on the same substrate without effecting control by means of the impurity concentration of the channel region. A semiconductor device is provided with a fully-depleted SOI MOSFET and a partially-depleted SOI MOSFET on the same SOI substrate through isolation by an element isolation film. The SOI substrate includes a buried oxide film and SOI layer provided in succession on a silicon substrate.

Abstract: A unit cell of a static random-access memory includes a laminated gate electrode structure adjacent to a diffusion layer. A top surface of the gate electrode structure is coated with a first silicide layer and the diffusion layer includes a second silicide layer. The second silicide layer is separated from the gate electrode structure by a distance that is the same as a width of a sidewall spacer on an opposite side of the gate electrode structure. The portion of the diffusion layer that is exposed between the second silicide layer and the gate electrode structure has a higher impurity concentration than the remainder of the diffusion layer to reduce or eliminate undesired leakage voltage.

Abstract: A semiconductor thin film structure includes source/drain regions and a channel region positioned between the source/drain regions. The semiconductor thin film structure extends directly on and in contact with a surface of an insulation region. At least one of the source/drain regions includes a semiconductor material region extending directly over and in contact with the surface of the insulation region and a refractory metal silicide layer extending directly on and in contact with the semiconductor material region. The refractory metal silicide layer has a first thickness which is equal to or thicker than a half of a second thickness of the channel region, thereby suppressing any substantive kink effect.

Abstract: The present invention provides a source/drain structure formed in a semiconductor layer which has source and drain regions of a first conductivity type and a body portion of a second conductivity type disposed between said source and drain regions. The body portion is positioned under a gate insulation film over which a gate electrode is provided. The source region has a first low resistive region which is lower in electrical resistivity than said source region and said drain region having a second low resistive region which is lower in electrical resistively than said source region. For the first present invention, it is important that a distance of an inside edge portion of the first low resistive region from a first interface between the source region and the body portion is shorter than a distance of an inside portion of the second low resistive region from a second interface between the drain region and the body portion.

Abstract: Disclosed is a method for fabricating semiconductor device, which has the steps of: forming a device separation region to section a first device forming region and a second device forming region on a substrate with a SOI structure; forming gate oxide film on the first and second device forming regions; introducing first conductivity type impurity and second conductivity type impurity into the first and second device forming regions to form a channel region of a first channel type transistor by the first conductivity type impurity and to form a source-drain region of the first channel type transistor by the second conductivity type impurity on at least the first device forming region; and introducing the first conductivity type impurity and the second conductivity type impurity selectively into the second device forming region to form a channel region and a source-drain region of a second channel type transistor on the second device forming region.