Patents by Inventor Klaas Bult
Klaas Bult has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6639430Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.Type: GrantFiled: February 27, 2002Date of Patent: October 28, 2003Assignee: Broadcom CorporationInventors: Klaas Bult, Rudy Van de Plassche, Jan Mulder
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Publication number: 20030194978Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.Type: ApplicationFiled: May 19, 2003Publication date: October 16, 2003Inventors: Pieter Vorenkamp, Klaas Bult, Frank Carr
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Publication number: 20030162521Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.Type: ApplicationFiled: March 17, 2003Publication date: August 28, 2003Applicant: Broadcom CorporationInventors: Pieter Vorenkamp, Klaas Bult, Frank Carr
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Patent number: 6591091Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.Type: GrantFiled: November 12, 1999Date of Patent: July 8, 2003Assignee: Broadcom CorporationInventors: Pieter Vorenkamp, Klaas Bult, Frank Carr
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Publication number: 20030107427Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.Type: ApplicationFiled: November 25, 2002Publication date: June 12, 2003Applicant: Broadcom CorporationInventors: Pieter Vorenkamp, Klaas Bult, Frank Carr
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Patent number: 6573851Abstract: A system and method for converting an analog input signal to a N-bit digital output signal. The invention comprises generating a plurality of reference voltage signals; pre-amplifying, separately, a difference between each of the plurality of reference voltage signals and an analog input signal using a plurality of cascaded, differential, switched-capacitor circuits to output a plurality of pre-amplified difference signals; and determining a zero-crossing result for each of the plurality of pre-amplified difference signals. Then one of a binary 1 and a binary 0 are assigned to each of the compared, pre-amplified signals. The binary 1's and 0's are encoded as an M-bit encoded signal, which is then decoded to output an N-bit digital output signal, wherein M is less that or equal to N.Type: GrantFiled: February 22, 2002Date of Patent: June 3, 2003Assignee: Broadcom CorporationInventor: Klaas Bult
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Publication number: 20030085829Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.Type: ApplicationFiled: December 16, 2002Publication date: May 8, 2003Applicant: Broadcom CorporationInventors: Klaas Bult, Chi-Hung Lin
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Patent number: 6549766Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.Type: GrantFiled: January 29, 2001Date of Patent: April 15, 2003Assignee: Broadcom CorporationInventors: Pieter Vorenkamp, Klaas Bult, Frank Carr
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Publication number: 20030054787Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.Type: ApplicationFiled: October 29, 2002Publication date: March 20, 2003Inventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Patent number: 6522279Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.Type: GrantFiled: June 20, 2002Date of Patent: February 18, 2003Assignee: Broadcom CorporationInventors: Klaas Bult, Chi-Hung Lin
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Patent number: 6504420Abstract: A compensation circuit compensates for the variation in the internal resistance of a multi-track inductor over temperature. The compensation circuit includes a dummy inductor that has the same temperature dependent resistance as that of the multi-track inductor that is to be compensated. A first field effect transistor is placed in series with the multi-track inductor that is to be compensated, and a second field effect transistor is placed in series with the dummy inductor, where the gates of the FETs are tied together. A control circuit provides a constant current for the dummy inductor and detects any changes in voltage of the dummy inductor over temperature. The control circuit includes a feedback loop that controls the gate voltage of both first and second FETs so as to compensate for the temperature dependent inductor resistance variations of both the dummy inductor and the multi-track inductor that is to be compensated.Type: GrantFiled: November 12, 1999Date of Patent: January 7, 2003Assignee: Broadcom CorporationInventors: Pieter Vorenkamp, Klaas Bult, Frank Carr
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Publication number: 20030001768Abstract: A system and method for converting an analog input signal to a N-bit digital output signal. The invention comprises generating a plurality of reference voltage signals; pre-amplifying, separately, a difference between each of the plurality of reference voltage signals and an analog input signal using a plurality of cascaded, differential, switched-capacitor circuits to output a plurality of pre-amplified difference signals; and determining a zero-crossing result for each of the plurality of pre-amplified difference signals. Then one of a binary 1 and a binary 0 are assigned to each of the compared, pre-amplified signals. The binary 1's and 0's are encoded as an M-bit encoded signal, which is then decoded to output an N-bit digital output signal, wherein M is less that or equal to N.Type: ApplicationFiled: February 22, 2002Publication date: January 2, 2003Applicant: Broadcom CorporationInventor: Klaas Bult
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Publication number: 20020196172Abstract: An M-bit folding/interpolating analog-to-digital converter (ADC) circuit, comprising a reference voltage generator, a converter, an interpolator, an amplifying stage, a comparator, and an encoder. The converter has an amplifier that receives at least one of a plurality of first reference voltage signals and outputs a plurality of coarse bits. The converter also has N-number of folding blocks, which output a plurality of folded signals. Each folding block comprises a plurality of capacitors, a differential amplifier and a feedback element. The folded signals output by the converter are then interpolated, amplified, compared and output as a plurality of fine bits. The encoder receives the coarse and fine bits and outputs the digital signal.Type: ApplicationFiled: February 11, 2002Publication date: December 26, 2002Applicant: Broadcom CorporationInventor: Klaas Bult
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Publication number: 20020196063Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.Type: ApplicationFiled: February 27, 2002Publication date: December 26, 2002Inventors: Klaas Bult, Rudy Van de Plassche, Jan Mulder
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Publication number: 20020167436Abstract: The output of each cell in an A-D converter on an IC chip is dependent upon the relative values of an input voltage and an individual one of progressive fractions of a reference voltage respectively introduced to the branches in a differential amplifier. To minimize output errors from cell mismatches, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals in the first branches, and the output terminals in the second branches, in successive pairs of cells. The impedances have relatively low values, particularly compared to the impedances of current sources connected to the branch output terminals. First and second resistive strips on the chip may be tapped at progressive positions to respectively define the impedances in the first and second sets.Type: ApplicationFiled: May 15, 2002Publication date: November 14, 2002Inventors: Klaas Bult, Aaron W. Buchwald
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Patent number: 6472940Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductors switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.Type: GrantFiled: November 13, 2000Date of Patent: October 29, 2002Assignee: Broadcom CorporationInventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Publication number: 20020154048Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.Type: ApplicationFiled: June 20, 2002Publication date: October 24, 2002Inventors: Klaas Bult, Chi-Hung Lin
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Patent number: 6414618Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.Type: GrantFiled: July 19, 2001Date of Patent: July 2, 2002Assignee: Broadcom CorporationInventors: Klaas Bult, Chi-Hung Lin
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Patent number: 6407692Abstract: The output of each cell in an A-D converter on an IC chip is dependent upon the relative values of an input voltage and an individual one of progressive fractions of a reference voltage respectively introduced to the branches in a differential amplifier. To minimize output errors from cell mismatches, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals in the first branches, and the output terminals in the second branches, in successive pairs of cells. The impedances have relatively low values, particularly compared to the impedances of current sources connected to the branch output terminals. First and second resistive strips on the chip may be tapped at progressive positions to respectively define the impedances in the first and second sets. One end of each strip may be connected to the opposite end of the other strip to define a closed impedance loop for minimizing averaging errors at the strip ends.Type: GrantFiled: October 31, 2000Date of Patent: June 18, 2002Assignee: Broadcom CorporationInventors: Klaas Bult, Aaron W. Buchwald
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Publication number: 20010041548Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.Type: ApplicationFiled: December 20, 2000Publication date: November 15, 2001Inventors: Klaas Bult, Rudy Van de Plassche, Pieter Vorenkamp, Arnoldus Venes