Abstract: Impurity elements are doped at a high concentration exceeding a thermodynamic equilibrium concentration into a solid material having an extremely small diffusion coefficient of the impurity element. A method for doping impurities includes steps for depositing source film made of material containing impurity elements with a film thickness on a surface of a solid target object (semiconductor substrate) made from the solid material. The film thickness is determined in consideration of irradiation time per light pulse and the energy density of the light pulse. The method also includes a step for irradiating the source film by the light pulse with the irradiation time and the energy density so as to dope the impurity elements into the target object at a concentration exceeding a thermodynamic equilibrium concentration.

Abstract: A semiconductor device includes a drift region of a first conductivity type, a channel forming region of a second conductivity type that is selectively provided in a first main surface of the drift region, a first main electrode region of the first conductivity type that is selectively provided in an upper part of the channel forming region, a second main electrode region of the second conductivity type that is provided in a second main surface of the drift region, and a high-concentration region of the first conductivity type that is provided in a portion of the drift region below the channel forming region so as to be separated from the channel forming region. The high-concentration region has a higher impurity concentration than the drift region and the total amount of first-conductivity-type impurities in the high-concentration region is equal to or less than 2.0×1012 cm?2.

Abstract: Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).

Abstract: When p-type impurities are implanted into a SiC substrate using a laser, controlling the concentration is difficult. A p-type impurity region is formed by a laser in a region where the control of the concentration in the SiC substrate is not necessary almost at all. A SiC semiconductor device having withstanding high voltage is manufactured at a lower temperature process compared to ion implantation process. A method of manufacturing a silicon carbide semiconductor device includes forming, on one main surface of a first conductivity-type silicon carbide substrate, a first conductivity-type drift layer having a lower concentration than that of the silicon carbide substrate; forming, on a front surface side of the drift layer, a second conductivity-type electric field control region by a laser doping technology; forming a Schottky electrode in contact with the drift layer; and forming, on the other main surface of the silicon carbide substrate, a cathode electrode.

Abstract: Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).

Abstract: Impurity elements are doped at a high concentration exceeding a thermodynamic equilibrium concentration into a solid material having an extremely small diffusion coefficient of the impurity element. A method for doping impurities includes steps for depositing source film made of material containing impurity elements with a film thickness on a surface of a solid target object (semiconductor substrate) made from the solid material. The film thickness is determined in consideration of irradiation time per light pulse and the energy density of the light pulse. The method also includes a step for irradiating the source film by the light pulse with the irradiation time and the energy density so as to dope the impurity elements into the target object at a concentration exceeding a thermodynamic equilibrium concentration.

Abstract: Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.

Abstract: A semiconductor device, including: a semiconductor substrate of a first conductivity type, the semiconductor substrate having an edge termination area adjacent to an outermost periphery thereof; an anode structure provided in a bottom surface of the semiconductor substrate; a cathode region of the first conductivity type selectively provided in a top surface of the semiconductor substrate at an inner side of the edge termination area; a cathode electrode on the cathode layer; and an isolation region of a second conductivity type in the outermost periphery of the semiconductor substrate, the isolation region having a vertically elongated shape such that a bottom of the isolation region is connected to an outermost periphery of the anode structure on the bottom surface of the semiconductor substrate and a top of the isolation region reaches the top surface of the semiconductor substrate.

Abstract: A semiconductor device includes a drift region of a first conductivity type, a channel forming region of a second conductivity type that is selectively provided in a first main surface of the drift region, a first main electrode region of the first conductivity type that is selectively provided in an upper part of the channel forming region, a second main electrode region of the second conductivity type that is provided in a second main surface of the drift region, and a high-concentration region of the first conductivity type that is provided in a portion of the drift region below the channel forming region so as to be separated from the channel forming region. The high-concentration region has a higher impurity concentration than the drift region and the total amount of first-conductivity-type impurities in the high-concentration region is equal to or less than 2.0×1012 cm?2.

Abstract: A trench gate MOS structure is provided on one main surface of a semiconductor substrate which will be an n? drift region. An n shell region is provided in the n? drift region so that it contacts a surface of a p base region close to the n? drift region forming the trench gate MOS structure. The n shell region has a higher impurity concentration than the n? drift region. The effective dose of n-type impurities in the n shell region is equal to or less than 5.0×1012 cm?2. The n? drift region has a resistivity to prevent a depletion layer, which is spread from a p collector region on the other main surface when reverse rated voltage is applied with an emitter as positive electrode, from reaching either n shell region or the bottom of a first trench, whichever is closer to the p collector region.

Abstract: In aspects of the invention, SiC reverse blocking MOSFET includes an active region including a MOS gate structure and a breakdown voltage structure portion surrounding the outer circumference of the active region, which are provided on the surface side of a SiC-n? drift layer that is grown on one main surface of a p+ SiC substrate. A p-type isolation region is provided on the side surface of the SiC-n? drift layer so as to surround the outer circumference of the breakdown voltage structure portion and to extend from the front surface of the SiC-n? drift layer to the p+ SiC substrate. A concave portion which reaches the SiC-n? drift layer through the p+ SiC substrate and has a bottom area corresponding to the area of the active region is provided in a region of the other main surface of the p+ SiC substrate which is opposite to the active region.

Abstract: A trench gate MOS structure is provided on one main surface of a semiconductor substrate which will be an n? drift region. An n shell region is provided in the n? drift region so that it contacts a surface of a p base region close to the n? drift region forming the trench gate MOS structure. The n shell region has a higher impurity concentration than the n? drift region. The effective dose of n-type impurities in the n shell region is equal to or less than 5.0×1012 cm?2. The n? drift region has a resistivity to prevent a depletion layer, which is spread from a p collector region on the other main surface when reverse rated voltage is applied with an emitter as positive electrode, from reaching either n shell region or the bottom of a first trench, whichever is closer to the p collector region.

Abstract: A power converter includes pairs of series-connected switching elements and, for each pair, a bidirectional switch that clamps the switching elements of the pair at the mid-point of a DC voltage that is supplied to the power converter. An abnormal voltage rise in a forward recovery process of the bidirectional switch is avoided by restraining an induced electromotive force developing across the bidirectional switch upon turning OFF of one of the semiconductor switching elements below the difference in voltage between the gate voltage at the start of the forward recovery process of the bidirectional switch and the gate threshold voltage that allows the maximum recovery current of the bidirectional switch to flow.

Abstract: Plural gate trenches are formed in the surface of an n-type drift region. A gate electrode is formed across a gate oxide film on the inner walls of the gate trenches. P-type base regions are selectively formed so as to neighbor each other in the gate trench longitudinal direction between neighboring gate trenches. An n-type emitter region is formed in contact with the gate trench in a surface layer of the p-type base regions. Also, a p-type contact region with a concentration higher than that of the p-type base region is formed in the surface layer of the p-type base region so as to be in contact with the gate trench side of the n-type emitter region. An edge portion on the gate trench side of the n-type emitter region terminates inside the p-type contact region.

Abstract: A power converter includes pairs of series-connected switching elements and, for each pair, a bidirectional switch that clamps the switching elements of the pair at the mid-point of a DC voltage that is supplied to the power converter. An abnormal voltage rise in a forward recovery process of the bidirectional switch is avoided by restraining an induced electromotive force developing across the bidirectional switch upon turning OFF of one of the semiconductor switching elements below the difference in voltage between the gate voltage at the start of the forward recovery process of the bidirectional switch and the gate threshold voltage that allows the maximum recovery current of the bidirectional switch to flow.

Abstract: A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n+-type field stop layer, in a direction parallel to the first major surface of the n-type main semiconductor layer. A substrate used for manufacturing the semiconductor device is fabricated by forming trenches in an n-type main semiconductor layer 1 and performing ion implantation and subsequent heat treatment to form an n+-type field stop layer in the bottom of the trenches. The trenches are then filled with a semiconductor doped more lightly than the n-type main semiconductor layer for forming extremely lightly doped n-type semiconductor layers. The manufacturing method is applicable with variations to various power semiconductor devices such as IGBT's, MOSFET's and PIN diodes.

Abstract: Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.

Abstract: A wide-band-gap reverse-blocking MOS-type semiconductor device includes a SiC n?-type drift layer; a p+-type substrate on the first major surface side of the drift layer; a trench extending through a p+-type substrate into the drift layer; a titanium electrode in the trench bottom that forms a Schottky junction with the SiC n?-type drift layer; an active section including a MOS-gate structure on the second major surface side of the drift layer facing to the area, in which the Schottky junctions are formed; a breakdown withstanding section surrounding the active section; and a trench isolation layer surrounding the breakdown withstanding section, the trench isolation layer extending from the second major surface of the drift layer into p+-type substrate and including insulator film buried therein. The device facilitates making a high current flow with a low ON-voltage and exhibits a very reliable reverse blocking capability.

Abstract: Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.

Abstract: A reverse blocking IGBT according to the invention can include a reverse breakdown withstanding region, p-type outer field limiting rings formed in a reverse breakdown withstanding region and an outer field plate connected to the outer field limiting rings, the outer field plate including a first outer field plate in contact with outer field limiting rings nearest to the active region and second outer field plates in contact with other outer field limiting rings. The first outer field plate having an active region side edge portion projecting toward the active region and second outer field plate having an edge area side edge portion projecting toward the edge area. The reverse blocking IGBT according to the invention can facilitate improving the withstand voltages thereof and reducing the area thereof.