Abstract: A semiconductor device is discloses that includes an n-type semiconductor substrate; an alternating conductivity type layer on semiconductor substrate, the alternating conductivity type layer including n-type drift regions and p-type partition regions arranged alternately; p-type channel regions on the alternating conductivity type layer; and trenches formed from the surfaces of the p-type channel regions down to respective n-type drift regions. The bottom of each trench is over the pn-junction between the p-type partition region and the n-type drift region. The semiconductor device facilitates preventing the on-resistance from increasing, obtaining a higher breakdown voltage, and reducing the variations caused in the characteristics thereof.

Abstract: A manufacturing method is provided for manufacturing a semiconductor apparatus including a main semiconductor device and a subsidiary semiconductor device, which facilitates preventing characteristics variations from causing and reducing the manufacturing costs.

Abstract: A reverse blocking IGBT according to the invention can include a reverse breakdown withstanding region, p-type outer field limiting rings formed in a reverse breakdown withstanding region and an outer field plate connected to the outer field limiting rings, the outer field plate including a first outer field plate in contact with outer filed limiting rings nearest to the active region and second outer field plates in contact with other outer field limiting rings. The first outer field plate having an active region side edge portion projecting toward the active region and second outer field plate having an edge area side edge portion projecting toward the edge area. The reverse blocking IGBT according to the invention can facilitate improving the withstand voltages thereof and reducing the area thereof.

Abstract: Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).

Abstract: A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

Abstract: A semiconductor device has a semiconductor substrate including an n-type high impurity concentration layer inhibiting a depletion layer from spreading, an n-type low impurity concentration drift layer, and a p-type high impurity concentration layer forming a p-n main junction between the drift layer. In the active region, an effective current flows in the direction of the thickness of the substrate. The device has an inclined trench that cuts the p-n main junction at a positive bevel angle from the semiconductor substrate surface on the side of the n-type high impurity concentration layer to penetrate through the substrate for separating it into chips. In the device, along the sidewall of the inclined trench in the n-type drift layer, an n-type surface region is formed with an impurity concentration lower than that in the n-type drift layer.

Abstract: A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

Abstract: A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n+-type field stop layer, in a direction parallel to the first major surface of the n-type main semiconductor layer. A substrate used for manufacturing the semiconductor device is fabricated by forming trenches in an n-type main semiconductor layer 1 and performing ion implantation and subsequent heat treatment to form an n+-type field stop layer in the bottom of the trenches. The trenches are then filled with a semiconductor doped more lightly than the n-type main semiconductor layer for forming extremely lightly doped n-type semiconductor layers. The manufacturing method is applicable with variations to various power semiconductor devices such as IGBT's, MOSFET's and PIN diodes.

Abstract: A power semiconductor device is provided, that realizes high-speed turnoff and soft switching at the same time, includes n-type main semiconductor layer including lightly doped n-type semiconductor layer and extremely lightly doped n-type semiconductor layer arranged alternately and repeatedly between p-type channel layer and field stop layer and in parallel to the first major surface of n-type main semiconductor layer. Extremely lightly doped n-type semiconductor layer is doped more lightly than lightly doped n-type semiconductor layer. Lightly doped n-type semiconductor layer prevents a space charge region from expanding at the time of turnoff. Extremely lightly doped n-type semiconductor layer expands the space charge region at the time of turnoff to eject electrons and holes quickly further to realize high-speed turnoff.

Abstract: A manufacturing method is provided for manufacturing a semiconductor apparatus including a main semiconductor device and a subsidiary semiconductor device, which facilitates preventing characteristics variations from causing and reducing the manufacturing costs.

Abstract: A semiconductor device equipped with a primary semiconductor element and a temperature detecting element for detecting a temperature of the primary semiconductor element. The device includes a first semiconductor layer of a first conductivity type that forms the primary semiconductor element. A second semiconductor region of a second conductivity type is provided in the first semiconductor layer. A third semiconductor region of the first conductivity type is provided in the second semiconductor region. The temperature detecting element is provided in the third semiconductor region and is separated from the first semiconductor layer by a PN junction.

Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.

Abstract: A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.

Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.

Abstract: A vertical and trench type insulated gate MOS semiconductor device includes a plurality of regions each being provided between adjacent ones of a plurality of the straight-line-like trenches arranged in parallel and forming a surface pattern of a plurality of straight lines. A plurality of first inter-trench surface regions are provided, each with an n+-type emitter region and a p+-type body region formed thereon, and the surfaces of regions are alternately arranged along the trench in the longitudinal direction thereof with an emitter electrode being in common contact with both of the surfaces of the n+-type emitter region and the p+-type body region. A plurality of second inter-trench surface regions are provided each of which is formed along the trench in the longitudinal direction thereof with one of the surface of the p base region and the surface of the n-type semiconductor substrate.

Abstract: A semiconductor device is disclosed which improves the breakdown voltage of a planar-type junction edge terminating structure. The device includes an n-type semiconductor substrate layer common to an active section and an edge terminating section. An n-type drift region is formed selectively on the n-type semiconductor substrate layer in the active section and a p-type partition region is formed selectively on the n-type semiconductor substrate layer in the active section. A p-type base/body region is formed on the n-type drift region and the partition region. A source electrode is connected electrically to the p-type base/body region. A p-type partition region is formed in the edge terminating section between the p-type base/body region and the scribe plane of the semiconductor device such that the p-type partition region in the edge terminating section surrounds the p-type base/body region. A drain electrode is connected electrically to the n-type semiconductor substrate layer.

Abstract: A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

Abstract: A semiconductor system includes a self arc-extinguishing device, and an IGBT that works as a thyristor when a current between a first terminal and a second terminal connected to a second well electrode is small, and as a bipolar transistor when that current is large, and automatically switches between them according to the magnitude of the current. The IGBT is formed with a first conductivity-type semiconductor substrate. On a surface layer of the substrate is a second conductivity-type well region to which a first well electrode is connected. A first conductivity-type emitter region, to which an emitter electrode is connected, is disposed on a surface layer in the well region. A control electrode is disposed through an insulating film partially covering the well and emitter regions. A second conductivity-type well layer, to which the second well electrode is connected, is disposed on a back surface side of the substrate.

Abstract: A semiconductor device and a method of forming thereof have a semiconductor substrate, an active region, and an inclined trench formed around the outer periphery of the active region. The semiconductor substrate at least includes an n-type high impurity concentration layer inhibiting a depletion layer from spreading, an n-type low impurity concentration drift layer, and a p-type high impurity concentration layer forming a p-n main junction between the drift layer, which are arranged in this order. In the active region, an effective current flows in the direction of the thickness of the substrate. The inclined trench cuts the p-n main junction at a positive bevel angle from the semiconductor substrate surface on the side of the n-type high impurity concentration layer to penetrate through the substrate for separating it into chips.

Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.