Patents by Inventor Koichi Yamashita

Koichi Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6052326
    Abstract: A semiconductor integrated circuit includes a circuit including a plurality of memory blocks connected in series and operating in synchronism with a clock signal, the circuit holding data in each of the memory blocks during a data-hold state and holding the data between adjacent ones of the memory blocks during a data-transition state. The semiconductor integrated circuit further includes a memory circuit inserted between at least two adjacent ones of the memory blocks and operating in synchronism with the clock signal, the memory circuit holding the data between the at least two adjacent ones of the memory blocks during the data-transition period.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: April 18, 2000
    Assignee: Fujitsu Limited
    Inventors: Shoichiro Kashiwakura, Koichi Yamashita
  • Patent number: 6032620
    Abstract: An air intake structure in a construction machine, comprising a radiator chamber, a radiator ventilating hole formed in an upper position of the radiator chamber, an air cleaner chamber formed in close proximity to the radiator chamber, an air cleaner ventilating hole formed in the ceiling surface of the air cleaner chamber, an intake duct disposed below the air cleaner ventilating hole and communicating with the radiator chamber, and an air cleaner disposed in close proximity to the ceiling surface of the air cleaner chamber at a position close to the intake duct. According to this air intake structure, not only the engine cooling efficiency can be enhanced to a satisfactory extent, but also a lower space in the air cleaner chamber can be fully utilized effectively.
    Type: Grant
    Filed: October 29, 1998
    Date of Patent: March 7, 2000
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Takashi Tsukiana, Kazuyuki Saki, Hiroaki Iwamitsu, Koichi Yamashita, Keiji Fujioka
  • Patent number: 6018559
    Abstract: A shift register having a plurality of circuit cells successively connected in a chain formation is proposed. Each of the circuit cells includes a first inversion gate, a first transmission gate, connected to an output of the first inversion gate, being switched by a clock, and a second inversion gate connected to an output of the first transmission gate. The circuit cell further includes a first P-channel transistor, connected between an output of the second inversion gate and an input of the first inversion gate, being switched by the clock, a second transmission gate, connected to the output of the second inversion gate, being switched by an inversion clock, and a second P-channel transistor, connected to the output of the first transmission gate, being switched by the inversion clock.
    Type: Grant
    Filed: December 16, 1996
    Date of Patent: January 25, 2000
    Assignee: Fujitsu Limited
    Inventors: Kengo Azegami, Koichi Yamashita
  • Patent number: 6015975
    Abstract: The present invention is a method of charged particle beam exposure wherein an area of an exposure pattern is exposed by irradiating a sample with a charged particle beam while moving said sample, comprising: a step of generating speed data including the speed distribution in a direction of movement of the sample in accordance with secondary data which is generated from a pattern data including at least data of the exposure pattern and data of an exposure position, and includes at least density information of the exposure pattern; and a step of irradiating the sample with the charged particle beam in accordance with the pattern data while being moved at variable speed in accordance with the speed data. According to the invention, the through-put is improved very much without any defect of the exposure.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: January 18, 2000
    Assignee: Fujitsu Limited
    Inventors: Kenichi Kawakami, Masahiko Susa, Kobayashi Katsuhiko, Akio Yamada, Koichi Yamashita, Naoki Nishio
  • Patent number: 6014300
    Abstract: A power source circuit includes switch for connecting and disconnecting a power source to and from a circuit proper; stabilizing means for suppressing a variation of an input voltage to stabilize the input voltage; voltage increasing means for increasing the input voltage in amplitude; switching means for controlling a voltage increasing operation; rectifying means for rectifying a switching waveform; smoothing means for smoothing a rectified waveform; and control means for controlling an output voltage to be constant in amplitude. In the power source circuit, the start of operating the power source circuit is delayed behind the start of supplying electric power. Therefore, it is prevent a power source circuit from failing to operate under the condition that a power source of a large internal resistance is coupled thereto, and the rush current, for example, causes the power source voltage drop.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: January 11, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Koichi Yamashita, Hiroaki Sugiura, Tetsuya Kuno, Narihiro Matoba
  • Patent number: 5968903
    Abstract: The present invention is directed to a method of using somatostatin or a somatostatin agonist to inhibit the proliferation of Helicobacter pylori (H. pylori), which comprises administering to a patient in need thereof an effective amount of said somatostatin or somatostatin agonist. Preferably, a somatostatin sub-type receptor 2 (SSTR-2) selective somatostatin agonist is administered in a method of this invention. The inhibition of H. pylori proliferation is useful in treating various gastroduodenal diseases such as peptic ulcers, gastric cancer and gastric lymphoma.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: October 19, 1999
    Assignee: Biomeasure, Incorporated
    Inventors: Hiroshi Kaneko, Terunori Mitsuma, Koichi Yamashita, Barry Morgan
  • Patent number: 5910466
    Abstract: The present invention relates to a catalyst for purifying an exhaust gas, and in particular provides a catalyst for purifying an exhaust gas using a complex oxide, which is not deteriorated in its purifying performance even in a lean atmosphere containing sulfur dioxide SO.sub.2 at temperatures as high as at least 1,000.degree. C., comprising at least one of the noble metals and one or at least two elements selected from the group consisting of alkaline earth metals and Group IIIA elements, and at least one member selected from the group consisting of iron, nickel and cobalt is supported in the surface portion of the catalyst, the catalyst further comprising, as a constituent element of the complex oxide, at least one element selected from the group consisting of iron, nickel and cobalt.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: June 8, 1999
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Koichi Yamashita, Mikio Murachi
  • Patent number: 5821550
    Abstract: A pattern density for each of regions on a wafer is calculated from circuit pattern data, and a stage speed suitable for the pattern density for each of the regions is determined. An acceleration is etermined from the difference between the stage speeds for two adjacent the regions, and a higher one of the stage speeds is corrected into a lower stage speed such that the determined acceleration becomes smaller than a predetermined value. Inflection points where the stage speeds change are found. A quadratic function interconnecting adjacent two of the inflection points is determined, and the inflection points are interconnected with a curve represented by the quadratic function, thereby determining a path of movement for the stage of an electron beam exposure system. The stage is controlled to move along the path of movement thus determined.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: October 13, 1998
    Assignee: Advantest Corporation
    Inventor: Koichi Yamashita
  • Patent number: 5798403
    Abstract: This invention provides a heat resistant thermoplastic resin composition comprising (A) 5 to 95 parts by weight of a polyamide resin, (B) 5 to 95 parts by weight of a copolymer containing an unsaturated carboxylic acid, comprising 40 to 80% by weight of an aromatic vinyl compound, 15 to 50% by weight of a vinyl cyanide compound, 0.1 to 20% by weight of an unsaturated carboxylic acid and 0 to 30% by weight of other vinyl compounds copolymerizable therewith, (C) 5 to 50 parts by weight of a graft copolymer, which is obtained by a graft polymerizing 60 to 5% by weight of a vinyl compound in the presence of 40 to 95% by weight of a diene rubber of an average particle size of 0.1 to 2.0 .mu.m, and, (D) 0.1 to 30 parts by weight of a kaolin to 100 parts by weight of the sum (A), (B) and (C). This heat resistant thermoplastic resin composition can provide molded articles which are superior in heat distortion resistance, impact strength and surface appearance, and has a high flowability in its molding.
    Type: Grant
    Filed: May 13, 1997
    Date of Patent: August 25, 1998
    Assignee: Kanegafuchi Kagaku Kogyo Kabushiki Kaisha
    Inventors: Koichi Yamashita, Hiroshi Kobayashi, Masahiro Asada
  • Patent number: 5506162
    Abstract: A semiconductor integrated circuit device provides; a master chip including a basic cell region having a plurality of basic cell arrays arranged thereon, for forming various kinds of circuits. An input/output cell region provides a plurality of input/output cells arranged along the periphery of the basic cell region. A first wiring layer is formed on the basic cell region and the input/output cell region via a first insulation layer and has contact holes at predetermined positions. The first wiring layer includes fixed wirings irrespective of the kind of circuit to be formed. A second wiring layer is formed on the first wiring layer via a second insulation layer having through holes at predetermined positions. The second wiring layer includes programmed wirings to specify the kind of circuit to be formed.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: April 9, 1996
    Assignee: Fujitsu Limited
    Inventors: Yoshio Hirose, Koichi Yamashita, Shigeki Kawahara, Shinji Sato, Takeshi Sasaki, Ataru Kumagai
  • Patent number: 5442246
    Abstract: A programmable logic circuit is provided with a plurality of logic cells including specific logic cells, at least two sub blocks, included in the specific logic cell, respectively having two or more inputs and one or more outputs and having only a predetermined combinational logic function by itself, and a switching circuit, included in the specific logic cell, and capable of independently connecting a path between the input and output of each sub block. An arbitrary combinational logic function and an arbitrary sequential logic function are realized by programming ON/OFF states of the switching circuit.
    Type: Grant
    Filed: September 29, 1993
    Date of Patent: August 15, 1995
    Assignee: Fujitsu Limited
    Inventors: Kengo Azegami, Koichi Yamashita
  • Patent number: 5424849
    Abstract: The video signal reproduction apparatus having two kinds of equalizing circuits to correct the level of a frequency-modulated luminance signal, that is, a first equalizing circuit which raises the level of the upper sideband range of the frequency-modulated luminance signal and a second equalizing circuit which raises the level of the lower sideband range of the frequency-modulated luminance signal, so that the part of the frequency-modulated luminance signal where a horizontal synchronizing signal is not modulated is processed by the first equalizing circuit, while the part of the frequency-modulated luminance signal where a horizontal synchronizing signal is modulated is processed by the second equalizing circuit.
    Type: Grant
    Filed: October 30, 1991
    Date of Patent: June 13, 1995
    Assignee: Mitsubishiki Denki Kabushiki Kaisha
    Inventors: Koichi Yamashita, Tomonori Oohashi, Masateru Nakano, Kazuhiro Kurisaki, Tomoki Yoshimura
  • Patent number: 5247456
    Abstract: A method and an apparatus is provided for forming a layout pattern of a semiconductor integrated circuit comprising automatically reforming a layout pattern by only carrying out a routing process, when a required layout pattern is the same as an existing layout pattern at the transistor-constitution level. Further, a method or an apparatus is provided for forming a layout pattern of a semiconductor integrated circuit comprising automatically reforming a layout pattern without analyzing the logical information down to the transistor-constitution level, when a required layout pattern is not the same as an existing layout pattern in the transistor-constitution level. Therefore, processing can be simplified and operation speed can be increased.
    Type: Grant
    Filed: November 8, 1988
    Date of Patent: September 21, 1993
    Assignee: Fujitsu Limited
    Inventors: Ryoichi Ohe, Koichi Yamashita
  • Patent number: 5234306
    Abstract: A panel storage feeder consists of a signature piling space, a panel feeding mechanism, a panel group storage mechanism and a panel group transfer mechanism. The panel feeding mechanism is disposed over the signature piling space to feed panels thereto one by one. The panel group storage mechanism is disposed at the side of the signature piling space and including the upper portion thereof provided at a level substantially equal to that of the panel feeding mechanism. The panel group transfer mechanism is disposed for transferring to a panel storage unit of the panel feeding mechanism from the upper portion of the panel group storage mechanism by a pair of hands moving therebetween. Thus, the panels are continuously and smoothly fed to the signature piling space.
    Type: Grant
    Filed: July 30, 1991
    Date of Patent: August 10, 1993
    Assignee: Kabushiki Kaisha Tokyo Kikai Seisakusho
    Inventor: Koichi Yamashita
  • Patent number: 5224033
    Abstract: A hydraulic actuator is operated using a manual operation device, operations from the manual operation device are stored in the path of an operation signal to a valve controller and these are read out as required and operations similar to those from the manual operation device are outputted to the hydraulic actuator so that repeated operations of the hydraulic actuator are performed automatically. Further, a vibration signal to the hydraulic actuator is added to the operation by the manual operation device and outputted so that operation that is not accurately performed by manual operation is made possible. In the case where repeated operations are performed continuously, a correction operation by the manual operation device is taken into account so that a correction operation which is varied every given amount is made simple. Thus, the present invention can be used where the digging process of a construction machine is made deeper every given amount.
    Type: Grant
    Filed: June 5, 1991
    Date of Patent: June 29, 1993
    Assignee: Kabushiki Kaisha Komatsu Seisakusho
    Inventors: Kentaro Nakamura, Takao Kamide, Kiyoshi Note, Koichi Yamashita, Shinji Maeda
  • Patent number: 5170342
    Abstract: A method and apparatus for automating a routine operation of an electronically controlled hydraulic-powered machine is provided. The apparatus is mounted on the hydraulic-powered machine to have the hydraulic-powered machine automatically and repetitively perform its simple routine operation. The present invention also provides a method and apparatus for automating a routine operation of an electronically controlled hydraulic-powered machine to perform an effective loading operation of a present amount of load.
    Type: Grant
    Filed: September 18, 1990
    Date of Patent: December 8, 1992
    Assignee: Kabushiki Kaisha Komatsu Seisakusho
    Inventors: Kentaro Nakamura, Kiyoshi Note, Koichi Yamashita, Shinji Maeda
  • Patent number: 4910735
    Abstract: A semiconductor integrated circuit comprises a plurality of integrated circuit blocks constructed on a wafer. The integrated circuit blocks are electrically connected to each other so as to form a system. Each of the integrated circuit blocks comprises a logic circuit for carrying out a logic operation, a pseudo-random pattern generating circuit for generating a pseudo-random pattern signal, a switching circuit for selecting either an input signal to be processed by the logic circuit or the pseudo-random pattern signal and a data compressing circuit for compressing an output data signal of the logic circuit. The switching circuit is responsive to a test enabling signal which is independently applied to each integrated circuit block so that each integrated circuit block is independently set to either a test mode or a normal mode, and outputs the selected signal to the logic circuit.
    Type: Grant
    Filed: December 17, 1987
    Date of Patent: March 20, 1990
    Assignee: Fujitsu Limited
    Inventor: Koichi Yamashita
  • Patent number: 4113434
    Abstract: A continuous sampling flow consisting of a plurality of gases is provided. The sampling of a plurality of gases according to the present invention comprises separately forming continuous gas streams of different gaseous phases, discharging said gas streams simultaneously and continuously into a common definite space in such a manner as to prevent them from mixing together, and sequentially positioning an inlet of open-sampling means successively in said discharged gas streams so that the gases in the individual gas streams are successively sampled and that a single stream formed by the sampled gases from the individual gas streams being in series one after another is taken out. In a preferred embodiment of the invention, the amount of gas sampled from each of said discharged gas streams is such that it will not disturb the discharged gas streams, e.g.
    Type: Grant
    Filed: July 27, 1976
    Date of Patent: September 12, 1978
    Assignee: Yanagimoto Seisakusho Co., Ltd.
    Inventors: Shinzo Tanaka, Shinichi Tsubamoto, Koichi Yamashita, Tadashi Eguchi, Kashirou Inoue
  • Patent number: 4072060
    Abstract: Sampling apparatus for installation on a predetermined path along which sets of printed and folded sheets are fed in overlapping relationship from the folder to the counter-stacker of a web-fed rotary press. The sampling apparatus comprises a divider mechanism which includes a divider blade and which is pivoted by a fluid actuated cylinder to and away from a working position, in which position the divider blade is disposed in the printed sheet path to cause several consecutive ones of the printed sheet sets to travel on one of its sides, where the path is open to a sample exit, and the succeeding printed sheet sets to travel on its other side. Immediately following the movement of the divider mechanism to the working position, an extractor mechanism comprising a pair of extractor blades is pivoted by another cylinder past the printed sheet path for delivering out of the sample exit at least the last of the several consecutive printed sheet sets travelling on the said one side of the divider blade.
    Type: Grant
    Filed: March 11, 1977
    Date of Patent: February 7, 1978
    Assignee: Kabushiki Kaisha Tokyo Kikai Seisakusho
    Inventors: Mitsuo Kitai, Koichi Yamashita