Patents by Inventor Koji Adachi
Koji Adachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160112588Abstract: Provided is a maintenance necessity estimation apparatus including a storage unit that stores in advance an estimation model and estimates first necessity information indicating a degree of necessity of a maintenance work with respect to the drive member in accordance with the output information, an acquisition section that acquires a second transit time and second feature information of an image processing apparatus which is an estimation target of second necessity information, and an estimation section that estimates necessity information of the image processing apparatus which is the estimation target using, as input information, a value corresponding to the second transit time and the second feature information acquired by the acquisition unit, using the estimation model stored in the storage unit.Type: ApplicationFiled: April 30, 2015Publication date: April 21, 2016Applicant: FUJI XEROX CO., LTD.Inventor: Koji ADACHI
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Patent number: 9300823Abstract: Provided is a maintenance necessity estimation apparatus including a storage unit that stores in advance an estimation model and estimates first necessity information indicating a degree of necessity of a maintenance work with respect to the drive member in accordance with the output information, an acquisition section that acquires a second transit time and second feature information of an image processing apparatus which is an estimation target of second necessity information, and an estimation section that estimates necessity information of the image processing apparatus which is the estimation target using, as input information, a value corresponding to the second transit time and the second feature information acquired by the acquisition unit, using the estimation model stored in the storage unit.Type: GrantFiled: April 30, 2015Date of Patent: March 29, 2016Assignee: FUJI XEROX CO., LTD.Inventor: Koji Adachi
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Patent number: 9286091Abstract: A semiconductor device includes an instruction decoder that decodes an instruction code and thereby generates instruction information, an execution unit that performs an operation based on the instruction information through pipeline processing, and a pipeline control unit that controls an order of the instruction code to be processed in the pipeline processing, in which the pipeline control unit includes a register for defining presence/absence of an authority to execute a first privilege program for each virtual machine, the first privilege program being to be executed on one virtual machine, refers to the register, and when the virtual machine that has issued the instruction code relating to the first privilege program has an authority to execute the first privilege program, instructs the execution unit to execute a process based on the instruction code relating to a second privilege program, based on an operation of the first privilege program.Type: GrantFiled: March 11, 2013Date of Patent: March 15, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koji Adachi, Hitoshi Suzuki
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Publication number: 20160041883Abstract: A computer system includes an interrupt controller to notify a bus error occurrence, and a multithreaded processor. The multithreaded processor includes a schedule register that settles a sequence of performing a plurality of virtual CPUs and stores data for virtual CPUs to be performed, and a virtual CPU execution portion that performs virtual CPUs according to a sequence settled by the schedule register. Virtual CPUs operate different operating systems (OS's) and include a first virtual CPU that operates a management OS to manage other OS's. When notified of bus error occurrence, the virtual CPU execution portion operates only the first virtual CPU regardless of an execution sequence settled in the schedule register. The first virtual CPU reinitializes a bus where an error occurred.Type: ApplicationFiled: October 20, 2015Publication date: February 11, 2016Inventors: Hirotaka Motai, Yasuhiro Tawara, Koji Adachi, Hitoshi Suzuki
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Patent number: 9244803Abstract: Provided is a failure predictive system, including a collection unit that collects information with respect to a job implemented in a monitored apparatus and information with respect to a job to be implemented, a calculating unit that calculates a probability of a failure occurrence in the monitored apparatus based on information with respect to the implemented job and information with respect to the job to be implemented which are collected by the collection unit, and an output unit that outputs information based on the probability when the probability calculated by the calculating unit is over a threshold value.Type: GrantFiled: September 2, 2014Date of Patent: January 26, 2016Assignee: FUJI XEROX CO., LTD.Inventors: Koji Adachi, Norikazu Yamada
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Patent number: 9240201Abstract: An enlarged substrate for a magnetic recording medium used in a data storage device such as a hard disc drive (HDD). In some embodiments, an apparatus includes a substrate for a magnetic recording disc for installation in a 3½ inch form factor hard disc drive, the substrate having an overall diameter of nominally from 96.9 mm to 100.4 mm. In other embodiments, an apparatus comprises a substrate for a magnetic recording disc for installation in a 2½ inch form factor hard disc drive, the substrate having an overall diameter of nominally from 66.9 mm to 71.8 mm. In other embodiments, a data storage device has a magnetic recording medium that uses an enlarged substrate as set forth above.Type: GrantFiled: August 24, 2015Date of Patent: January 19, 2016Assignee: Seagate Technology LLCInventors: Koji Adachi, Ian J. Beresford, Thomas Y. Chang, Kuo Hsing Hwang, James Hennessy, David Perez
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Publication number: 20150364149Abstract: An enlarged substrate for a magnetic recording medium used in a data storage device such as a hard disc drive (HDD). In some embodiments, an apparatus includes a substrate for a magnetic recording disc for installation in a 3- 1/2 inch form factor hard disc drive, the substrate having an overall diameter of nominally from 96.9 mm to 100.4 mm. In other embodiments, an apparatus comprises a substrate for a magnetic recording disc for installation in a 2- 1/2 inch form factor hard disc drive, the substrate having an overall diameter of nominally from 66.9 mm to 71.8 mm. In other embodiments, a data storage device has a magnetic recording medium that uses an enlarged substrate as set forth above.Type: ApplicationFiled: August 24, 2015Publication date: December 17, 2015Inventors: Koji Adachi, Ian J. Beresford, Thomas Y. Chang, Kuo Hsing Hwang, James Hennessy, David Perez
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Patent number: 9176756Abstract: There is a need to provide a computer system capable of preventing a failure from propagating and recovering from the failure. VCPU#0 through VCPU#2 each operate different OS's. VCPU#0 operates a management OS that manages the other OS's. When notified of bus error occurrence, a virtual CPU execution portion 201 operates only VCPU#0 regardless of an execution sequence stored in schedule register A. VCPU#0 reinitializes a bus where an error occurred.Type: GrantFiled: May 23, 2013Date of Patent: November 3, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hirotaka Motai, Yasuhiro Tawara, Koji Adachi, Hitoshi Suzuki
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Patent number: 9147421Abstract: An enlarged substrate for a magnetic recording medium used in a data storage device such as a hard disc drive (HDD). In some embodiments, an apparatus includes a substrate for a magnetic recording disc for installation in a 3½ inch form factor hard disc drive, the substrate having an overall diameter of nominally from 96.9 mm to 100.4 mm. In other embodiments, an apparatus comprises a substrate for a magnetic recording disc for installation in a 2½ inch form factor hard disc drive, the substrate having an overall diameter of nominally from 66.9 mm to 71.8 mm. In other embodiments, a data storage device has a magnetic recording medium that uses an enlarged substrate as set forth above.Type: GrantFiled: November 24, 2014Date of Patent: September 29, 2015Assignee: Seagate Technology LLCInventors: Koji Adachi, Ian J. Beresford, Thomas Y. Chang, Kuo Hsing Hwang, Jim P. Hennessy, David Perez
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Publication number: 20150227447Abstract: Provided is a failure predictive system, including a collection unit that collects information with respect to a job implemented in a monitored apparatus and information with respect to a job to be implemented, a calculating unit that calculates a probability of a failure occurrence in the monitored apparatus based on information with respect to the implemented job and information with respect to the job to be implemented which are collected by the collection unit, and an output unit that outputs information based on the probability when the probability calculated by the calculating unit is over a threshold value.Type: ApplicationFiled: September 2, 2014Publication date: August 13, 2015Inventors: Koji ADACHI, Norikazu YAMADA
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Publication number: 20150222775Abstract: Provided is a parameter setting system, including a storage unit that memorizes a history of parameter values in an image forming apparatus in association with a type of paper, an acquiring unit that acquires a trend of parameter values in plural image forming apparatuses of the same type with the image forming apparatus with respect to each type of plural other paper sheets in which the number of types of switched paper and the number of histories are greater than or equal to a threshold value, and a calculating unit that calculates a parameter value to be set with respect to the type of switched paper based on the trend of parameter values acquired with respect to the type of switched paper and each type of the plural other paper sheets, and the history corresponding to each type of the plural other paper sheets.Type: ApplicationFiled: August 25, 2014Publication date: August 6, 2015Inventor: Koji ADACHI
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Patent number: 9098336Abstract: A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a first thread scheduler that outputs a first thread selection signal, the first thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads according to a priority rank, the priority rank being established in advance for each of the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the first thread selection signal and outputs an instruction generated by the selected hardware thread, and an execution pipeline that executes an instruction output from the first selector. Whenever the hardware thread is executed in the execution pipeline, the first scheduler updates the priority rank for the executed hardware thread and outputs the first thread selection signal in accordance with the updated priority rank.Type: GrantFiled: September 14, 2012Date of Patent: August 4, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koji Adachi, Teppei Oomoto
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Publication number: 20150077877Abstract: An enlarged substrate for a magnetic recording medium used in a data storage device such as a hard disc drive (HDD). In some embodiments, an apparatus includes a substrate for a magnetic recording disc for installation in a 3½ inch form factor hard disc drive, the substrate having an overall diameter of nominally from 96.9 mm to 100.4 mm. In other embodiments, an apparatus comprises a substrate for a magnetic recording disc for installation in a 2½ inch form factor hard disc drive, the substrate having an overall diameter of nominally from 66.9 mm to 71.8 mm. In other embodiments, a data storage device has a magnetic recording medium that uses an enlarged substrate as set forth above.Type: ApplicationFiled: November 24, 2014Publication date: March 19, 2015Inventors: Koji Adachi, Ian J. Beresford, Thomas Y. Chang, Kuo Hsing Hwang, Jim P. Hennessy, David Perez
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Patent number: 8896964Abstract: An enlarged substrate for a magnetic recording medium used in a data storage device such as a hard disc drive (HDD). In some embodiments, an apparatus includes a substrate for a magnetic recording disc for installation in a 3½ inch form factor hard disc drive, the substrate having an overall diameter of nominally from 96.9 mm to 100.4 mm. In other embodiments, an apparatus comprises a substrate for a magnetic recording disc for installation in a 2½ inch form factor hard disc drive, the substrate having an overall diameter of nominally from 66.9 mm to 71.8 mm. In other embodiments, a data storage device has a magnetic recording medium that uses an enlarged substrate as set forth above.Type: GrantFiled: October 2, 2013Date of Patent: November 25, 2014Assignee: Seagate Technology LLCInventors: Koji Adachi, Ian J. Beresford, Thomas Y. Chang, Kuo Hsing Hwang, Jim P. Hennessy, David Perez
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Publication number: 20140340790Abstract: An enlarged substrate for a magnetic recording medium used in a data storage device such as a hard disc drive (HDD). In some embodiments, an apparatus includes a substrate for a magnetic recording disc for installation in a 3½ inch form factor hard disc drive, the substrate having an overall diameter of nominally from 96.9 mm to 100.4 mm. In other embodiments, an apparatus comprises a substrate for a magnetic recording disc for installation in a 2½ inch form factor hard disc drive, the substrate having an overall diameter of nominally from 66.9 mm to 71.8 mm. In other embodiments, a data storage device has a magnetic recording medium that uses an enlarged substrate as set forth above.Type: ApplicationFiled: October 2, 2013Publication date: November 20, 2014Applicant: Seagate Technologies LLCInventors: Koji Adachi, Ian J. Beresford, Thomas Y. Chang, Kuo Hsing Hwang, Jim P. Hennessy, David Perez
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Patent number: 8800205Abstract: A door opening-and-closing apparatus for a vehicle includes a rotatably driven drum, a first cable and a second cable, which cables are wound around the drum, a rotating shaft, a first pulley supported by the rotating shaft, a second pulley supported by the rotating shaft, an attachment member supporting the rotating shaft, a rigid protruding portion integral with one of the first and second pulleys, and an annular recessed portion integrally formed in the other one of the first and second pulleys. When the first and second pulleys are correctly assembled on the rotating shaft, a relative rotation between the first and second pulleys is allowed, and when the first and second pulleys are not correctly assembly on the rotating shaft, the predetermined length of the rotating shaft is not sufficient to support both the first and second pulleys.Type: GrantFiled: December 23, 2009Date of Patent: August 12, 2014Assignee: Aisin Seiki Kabushiki KaishaInventors: Junji Yamaguchi, Koji Adachi, Masayuki Uchitsunemi
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Publication number: 20140109098Abstract: The scheduler performs thread scheduling of repeating processings of specifying each hardware thread included in a first group among the multiple hardware threads for the number of times set up in advance for the hardware thread, and of specifying any one of the hardware threads in a second group for the number of times set up in advance for the second group that includes other hardware threads. Moreover, when the hardware thread in the first group specified by the thread scheduling is nondispatchable, the scheduler performs rescheduling of respecifying the hardware thread in the second group instead of the hardware thread in the first group.Type: ApplicationFiled: October 15, 2013Publication date: April 17, 2014Applicant: Renesas Electronics CorporationInventors: Junichi SATO, Koji Adachi, Yousuke Nakamura
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Publication number: 20140089938Abstract: A multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal in accordance with a schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads, and a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread. The thread scheduler specifies execution of at least one hardware thread pre-selected among the plurality of hardware threads in a predetermined first execution period, and specifies execution of a variably selected hardware thread in a second execution period other than the first execution period. A time ratio between the predetermined first execution period and the second execution period is set according to processing requests.Type: ApplicationFiled: November 27, 2013Publication date: March 27, 2014Applicant: Renesas Electronics CorporationInventors: Koji Adachi, Kazunori Miyamoto
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Publication number: 20130332717Abstract: A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a first thread scheduler that continuously outputs a thread selection signal uniformly in a first period of a cycle of the first schedule pattern in accordance with a first schedule pattern or continuously outputs the thread selection signal uniformly in a second period of a cycle of the second schedule pattern in accordance with a second schedule pattern, the thread selection signal designating a hardware thread to be executed in a next execution cycle from among the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread from among the plurality of hardware threads, and an execution pipeline that executes an instruction output from the first selector.Type: ApplicationFiled: August 12, 2013Publication date: December 12, 2013Applicant: Renesas Electronics CorporationInventors: Koji Adachi, Toshiyuki Matsunaga
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Publication number: 20130332925Abstract: There is a need to provide a computer system capable of preventing a failure from propagating and recovering from the failure. VCPU#0 through VCPU#2 each operate different OS's. VCPU#0 operates a management OS that manages the other OS's. When notified of bus error occurrence, a virtual CPU execution portion 201 operates only VCPU#0 regardless of an execution sequence stored in schedule register A. VCPU#0 reinitializes a bus where an error occurred.Type: ApplicationFiled: May 23, 2013Publication date: December 12, 2013Applicant: Renesas Electronics CorporationInventors: Hirotaka Motai, Yasuhiro Tawara, Koji Adachi, Hitoshi Suzuki