Patents by Inventor Koji Adachi

Koji Adachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8607030
    Abstract: A multi-thread processor in accordance with an exemplary aspect of the present invention includes a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal TSEL designating a hardware thread to be executed in a next execution cycle, a first selector that outputs an instruction generated by a hardware thread selected according to the thread selection signal, and an execution pipeline that executes an instruction output from the first selector, wherein the thread scheduler specifies execution of at least one hardware thread selected in a fixed manner in a predetermined first execution period, and specifies execution of an arbitrary hardware thread in a second execution period.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: December 10, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Adachi, Kazunori Miyamoto
  • Publication number: 20130297916
    Abstract: A related art semiconductor device suffers from a problem that a processing capacity is decayed by switching an occupied state for each partition. A semiconductor device according to the present invention includes an execution unit that executes an arithmetic instruction, and a scheduler including multiple first setting registers each defining a correspondence relationship between hardware threads and partitions, and generates a thread select signal on the basis of a partition schedule and a thread schedule. The scheduler outputs a thread select signal designating a specific hardware thread without depending on the thread schedule as the partition indicated by a first occupation control signal according to a first occupation control signal output when the execution unit executes a first occupation start instruction.
    Type: Application
    Filed: April 9, 2013
    Publication date: November 7, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Hitoshi Suzuki, Koji Adachi
  • Patent number: 8564802
    Abstract: An image defect inspection apparatus includes a supply unit, an acquiring unit, an inspection unit and an adjustment unit. The supply unit supplies a test image corresponding to an inferred image defect regarding an image forming unit that forms an image on a recording material, to the image forming unit to form the test image on the recording material. The acquiring unit acquires a scanned image obtained by scanning the recording material on which the test image is formed. The inspection unit compares the scanned image acquired with the test image and inspects as to whether or not the inferred image defect is in the scanned image. The adjustment unit adjusts a value of a setting item which is defined as an adjust target regarding the inferred image defect, so as to enhance detectability of the inferred image defect in the inspection.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: October 22, 2013
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Koji Adachi
  • Patent number: 8560812
    Abstract: A multithread execution device includes: a program memory in which a plurality of programs are stored; an instruction issue unit that issues an instruction retrieved from the program memory; an instruction execution unit that executes the instruction; a target execution speed information memory that stores target execution speed information of the instruction; an execution speed monitor that monitors an execution speed of the instruction; a feedback control unit that commands the instruction issue unit to issue the instruction such that the execution speed of the instruction approximately corresponds to the target execution speed information.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: October 15, 2013
    Assignees: Toyota Jidosha Kabushiki Kaisha, Renesas Electronics Corporation
    Inventors: Tetsuaki Wakabayashi, Koji Adachi, Kazuya Okamoto
  • Publication number: 20130263129
    Abstract: A semiconductor device includes an instruction decoder that decodes an instruction code and thereby generates instruction information, an execution unit that performs an operation based on the instruction information through pipeline processing, and a pipeline control unit that controls an order of the instruction code to be processed in the pipeline processing, in which the pipeline control unit includes a register for defining presence/absence of an authority to execute a first privilege program for each virtual machine, the first privilege program being to be executed on one virtual machine, refers to the register, and when the virtual machine that has issued the instruction code relating to the first privilege program has an authority to execute the first privilege program, instructs the execution unit to execute a process based on the instruction code relating to a second privilege program, based on an operation of the first privilege program.
    Type: Application
    Filed: March 11, 2013
    Publication date: October 3, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Koji ADACHI, Hitoshi Suzuki
  • Patent number: 8539203
    Abstract: In an exemplary aspect, the present invention provides a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal in accordance with a first or second schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread, and an execution pipeline that executes an instruction output from the first selector, wherein when the multi-thread processor is in a first state, the thread scheduler selects the first schedule, and when the multi-thread processor is in a second state, the thread scheduler selects the second schedule.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Adachi, Toshiyuki Matsunaga
  • Patent number: 8531744
    Abstract: An image defect diagnostic system includes: a memory that stores an image density threshold set for each of partial regions in a test target image being a test target for an image defect and set as a criteria for judging whether or not each of the partial regions has an image defect, and that stores a positional information piece indicating a position of corresponding one of the partial regions in the test target image, while associating the image density threshold and the positional information piece with each other; and a diagnostic unit that compares an image data piece of each of the partial regions generated by scanning the test target image with the image density threshold set for corresponding one of the partial regions stored in the memory, to diagnose whether or not an image defect occurs in the test target image.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: September 10, 2013
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Koji Adachi
  • Patent number: 8407387
    Abstract: A first exemplary aspect of an embodiment of the present invention is a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, and an interrupt controller that determines whether or not an input interrupt request signal is associated with one or more than one of the plurality of hardware threads, and when the input interrupt request signal is associated, assigns the interrupt request to an associated hardware thread.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: March 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Adachi, Kazunori Miyamoto
  • Patent number: 8405854
    Abstract: A monitoring device includes: a receiving unit that receives information including first use mode information transmitted from a first information processing device; a memory unit that stores the received first use mode information; a creating unit that creates, when the receiving unit receives trouble information together with the first use mode information, a trouble prediction formula corresponding to the trouble information using second use mode information of a second information processing device in which the same trouble as that indicated in the trouble information has occurred; a storing unit that stores the created trouble prediction formula; and a determining unit that determines, when the receiving unit receives third use mode information of a third information processing device, whether or not a trouble in the third information processing device occurs in a high probability based on the stored trouble prediction formula and the received third use mode information.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: March 26, 2013
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Noriyuki Matsuda, Masayasu Takano, Akiko Seta, Koji Adachi, Kaoru Yasukawa, Tetsuichi Satonaga
  • Patent number: 8403448
    Abstract: A medium transport device includes a sensor unit, a timing data collection unit, and a sampling resolution changing unit. The sensor unit is provided in a transport path of a print recording medium to detect a transport timing of the print recording medium. A timing data collection unit receives an output from the sensor unit and samples the output at a sampling interval as timing data. A sampling resolution changing unit changes the sampling interval.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: March 26, 2013
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Kaoru Yasukawa, Koji Adachi, Norikazu Yamada, Koki Uwatoko, Tetsuichi Satonaga, Shigehiro Furukawa
  • Patent number: 8405870
    Abstract: An image processing apparatus includes a determination unit determining, based on a pixel value of a prescribed background color area in image data obtained by inputting a printed image, and based on information regarding a color of a toner used in printing the image, whether or not the background color of the image corresponds to the color of the toner.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: March 26, 2013
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Koki Uwatoko, Koji Adachi, Kaoru Yasukawa, Norikazu Yamada, Shigehiro Furukawa, Tetsuichi Satonaga
  • Patent number: 8373881
    Abstract: An image formation apparatus, which includes: a detector unit that detects a status of consumables; a prediction unit that predicts a run-out timing of the consumables on the basis of the status detected by the detector unit; a transmission unit that transmits the status detected by the detector unit to a management apparatus as consumables information; a reception unit that receives run-out timing information indicating a run-out timing predicted by the management apparatus on the basis of the consumables information transmitted by the transmission unit; and a notification unit that notifies the run-out timing of the consumables on the basis of the run-out timing information received by the reception unit if communication with the management apparatus is possible, or notifies the run-out timing of the consumables on the basis of the run-out timing predicted by the prediction unit if communication with the management apparatus is not possible.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: February 12, 2013
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Akiko Seta, Noriyuki Matsuda, Masayasu Takano, Koji Adachi, Kaoru Yasukawa, Tetsuichi Satonaga
  • Patent number: 8365179
    Abstract: A multi-thread processor in accordance with an exemplary aspect of the present invention includes a plurality of hardware threads each of which generates an independent instruction flow, a first thread scheduler that outputs a first thread selection signal designating a hardware thread to be executed in the next execution cycle, a first selector that outputs an instruction generated by the selected hardware thread according to the first thread selection signal, and an execution pipeline that executes an instruction output from the first selector, wherein whenever a hardware thread is executed in the execution pipeline, the first thread scheduler updates the priority rank of the executed hardware thread and outputs the first thread selection signal in accordance with the updated priority rank.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: January 29, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Adachi, Teppei Oomoto
  • Patent number: 8355641
    Abstract: A paper wrinkle sign monitoring device includes: at least one timing detecting unit that is set on a transport path of a printing medium, and that detects transport timing of the printing medium; and a sign output unit that detects a sign of paper wrinkle generation in the transporting time of the printing medium based on the transport timing of the printing medium detected by the timing detecting unit, and that outputs the sign.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: January 15, 2013
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Koji Adachi, Kaoru Yasukawa, Shigehiro Furukawa, Norikazu Yamada, Koki Uwatoko, Tetsuichi Satonaga
  • Publication number: 20130013900
    Abstract: A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a first thread scheduler that outputs a first thread selection signal, the first thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads according to a priority rank, the priority rank being established in advance for each of the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the first thread selection signal and outputs an instruction generated by the selected hardware thread, and an execution pipeline that executes an instruction output from the first selector. Whenever the hardware thread is executed in the execution pipeline, the first scheduler updates the priority rank for the executed hardware thread and outputs the first thread selection signal in accordance with the updated priority rank.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Koji ADACHI, Teppei Oomoto
  • Patent number: 8326564
    Abstract: A detected data processing apparatus includes a selecting unit that calculates mutual correlation between a plurality of groups of detected data acquired from a detecting unit that detects an operational state of a circuit board, and then selects as analysis data the detected data of a group whose value indicating correlation with other groups is smaller than a threshold value set up in advance; and a first calculating unit that calculates a first Mahalanobis distance on a basis of a first Mahalanobis space generated by using the analysis data selected by the selecting unit from the detected data obtained when a normal circuit board is operated and on a basis of the detected data obtained when a circuit board of diagnosis target is operated.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: December 4, 2012
    Assignee: Fuji Xerox Co., Ltd
    Inventors: Tetsuichi Satonaga, Koji Adachi, Kaoru Yasukawa, Norikazu Yamada, Koki Uwatoko, Shigehiro Furukawa
  • Patent number: 8290893
    Abstract: According to an aspect of the present invention, there is provided a failure diagnosis system including: a causal relationship information storage unit configured to store causal relationship information representing a causal relationship between events regarding a diagnosis-target apparatus, the causal relationship information including: common causal relationship information that is commonly used in a plurality of types of failure diagnosis regarding the diagnosis-target apparatus; and specific causal relationship information that is used in each specific type of failure diagnosis among the plurality of types of failure diagnosis; and a diagnosis execution unit configured to selectively execute the plural types of failure diagnosis by using a combined causal relationship information that is a combination of the common causal relationship information and a piece of the specific causal relationship information corresponding to a diagnosis-target type of failure diagnosis.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: October 16, 2012
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Norikazu Yamada, Koji Adachi, Kaoru Yasukawa, Shigehiro Furukawa, Koki Uwatoko, Tetuichi Satonaga
  • Patent number: 8275271
    Abstract: An image forming apparatus includes a prediction unit, an inquiry unit and a request unit. The inquiry unit judges whether or not the prediction unit deals with a type of a consumable item used in image formation processing. The request unit transmits use history information to a consumable item management apparatus and requests the consumable item management apparatus to predict a remaining usable period of the consumable item when the inquiry unit judges the prediction unit does not deal with the type of the consumable item in the image formation processing. The use history information indicates a use history of the consumable item. The prediction unit predicts the remaining usable period of the consumable item using the use history information in the image formation processing when the inquiry unit judges the first prediction unit deals with the type of the consumable item used in image formation processing.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: September 25, 2012
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Tetsuichi Satonaga, Masayasu Takano, Noriyuki Matsuda, Akiko Seta, Koji Adachi, Kaoru Yasukawa
  • Patent number: 8265892
    Abstract: A management apparatus includes: a managing unit that manages production information corresponding to each of a plurality of information processing devices; a specifying unit that specifies, based on a defect notice for at least one component and the production information on the managed information processing devices, at least one of the information processing devices using the component; a state judging unit that judges whether each information processing device is in an operable state where a processing function of each information processing device is operable in an environment in which the processing function of each information processing device is provided; and an operation restricting unit that performs operation restriction for the processing function of each information processing device according to the defect notice if the state judging unit judges that each information processing device is in the operable state.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: September 11, 2012
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Noriyuki Matsuda, Masayasu Takano, Akiko Seta, Koji Adachi, Kaoru Yasukawa, Tetsuichi Satonaga
  • Patent number: 8219231
    Abstract: A quality control method includes: extracting, from a time series distribution of troubles that have occurred in electronic equipments, a first characteristics of states of occurrence of the troubles; specifying one or more parts included in the electronic equipments, the parts being involved with the troubles; extracting, from another time series distribution of a rate of use corresponding to each of suppliers which supply the specified parts, a second characteristics of the parts; and specifying one or more of the suppliers supplying the parts correlated to the troubles based on a correlation between the extracted first characteristics and the extracted second characteristics.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: July 10, 2012
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Tetsuichi Satonaga, Masayasu Takano, Noriyuki Matsuda, Akiko Seta, Koji Adachi, Kaoru Yasukawa