Patents by Inventor Koji Takemura
Koji Takemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8237281Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: GrantFiled: January 4, 2011Date of Patent: August 7, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Publication number: 20120181670Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.Type: ApplicationFiled: March 23, 2012Publication date: July 19, 2012Applicant: Panasonic CorporationInventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
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Patent number: 8212366Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.Type: GrantFiled: October 27, 2010Date of Patent: July 3, 2012Assignee: Panasonic CorporationInventors: Manabu Ohnishi, Koji Takemura, Noriyuki Nagai, Hoyeun Huh, Tomoyuki Nakayama, Atsushi Doi
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Patent number: 8164163Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.Type: GrantFiled: February 12, 2008Date of Patent: April 24, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
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Publication number: 20120080780Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.Type: ApplicationFiled: December 12, 2011Publication date: April 5, 2012Applicant: Panasonic CorporationInventors: Koji TAKEMURA, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
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Publication number: 20120069211Abstract: An image pickup apparatus is provided with: an optical system including a lens or a reflecting mirror; an image pickup device having a light-receiving surface on which light rays from the optical system are focused and a plurality of light-receiving pixels which generate charges on the light-receiving surface by the light rays; a bias voltage generation unit which supplies power to the image pickup device; a signal processing unit which processes a signal output from the image pickup device and outputs the processed signal as image data; and a control unit which inputs into the image pickup device a driving clock that controls transmission of the charges generated in the light-receiving pixels of the image pickup device. The image pickup device is bent so that distortion aberration present in the optical system is eliminated.Type: ApplicationFiled: May 12, 2010Publication date: March 22, 2012Applicant: NEC TOSHIBA Space Systems, Ltd.Inventors: Koji Takemura, Kazuhide Noguchi, Takashi Sakashita
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Patent number: 8102056Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.Type: GrantFiled: August 29, 2006Date of Patent: January 24, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
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Publication number: 20110266540Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.Type: ApplicationFiled: July 8, 2011Publication date: November 3, 2011Applicant: Panasonic CorporationInventors: Masao TAKAHASHI, Koji TAKEMURA, Toshihiko SAKASHITA, Tadaaki MIMURA
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Patent number: 7999256Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.Type: GrantFiled: September 11, 2008Date of Patent: August 16, 2011Assignee: Panasonic CorporationInventors: Masao Takahashi, Koji Takemura, Toshihiko Sakashita, Tadaaki Mimura
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Publication number: 20110095430Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: ApplicationFiled: January 4, 2011Publication date: April 28, 2011Applicant: PANASONIC CORPORATIONInventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Publication number: 20110037173Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.Type: ApplicationFiled: October 27, 2010Publication date: February 17, 2011Applicant: PANASONIC CORPORATIONInventors: Manabu OHNISHI, Koji TAKEMURA, Noriyuki NAGAI, Hoyeun HUH, Tomoyuki NAKAYAMA, Atsushi DOI
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Patent number: 7888801Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: GrantFiled: April 27, 2009Date of Patent: February 15, 2011Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Publication number: 20110024882Abstract: A semiconductor device includes a semiconductor substrate, a diffusion layer conductive film formed on the semiconductor substrate, an interlayer insulating film layered on the semiconductor substrate, an interconnect pattern and a via pattern formed in the interlayer insulating film, a plurality of circuit regions formed in the semiconductor substrate, and a scribe region formed around the circuit regions and separating the circuit regions from each other. The diffusion layer conductive film is not formed at least in a region to which laser light is emitted in the scribe region.Type: ApplicationFiled: October 8, 2010Publication date: February 3, 2011Applicant: PANASONIC CORPInventors: Koji TAKEMURA, Takahiro Kumakawa, Yoshihiro Matsushima
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Patent number: 7847418Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.Type: GrantFiled: January 15, 2010Date of Patent: December 7, 2010Assignee: Panasonic CorporationInventors: Manabu Ohnishi, Koji Takemura, Noriyuki Nagai, Hoyeun Huh, Tomoyuki Nakayama, Atsushi Doi
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Publication number: 20100117083Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.Type: ApplicationFiled: January 15, 2010Publication date: May 13, 2010Applicant: Panasonic CorporationInventors: Manabu OHNISHI, Koji Takemura, Noriyuki Nagai, Hoyeun Huh, Tomoyuki Nakayama, Atsushi Doi
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Patent number: 7696607Abstract: A semiconductor device includes: a circuit region having a function element formed on a semiconductor substrate; a scribe region located between the circuit region and another circuit region formed spaced from the circuit region, the scribe region including a cutting region and non-cutting regions provided at both sides of the cutting region; a first interlayer insulating film formed in the scribe region on the semiconductor substrate; a first dummy pattern made of conductive material and formed in the first interlayer insulating film in the cutting region; and a second dummy pattern made of conductive material and formed in the first interlayer insulating film in each of the non-cutting regions. The ratio, per unit area, of the area of the first dummy pattern to the area of the cutting region is lower than the ratio, per unit area, of the area of the second dummy pattern to the area of the non-cutting regions.Type: GrantFiled: August 9, 2007Date of Patent: April 13, 2010Assignee: Panasonic CorporationInventors: Hikari Sano, Masao Takahashi, Hiroshige Hirano, Koji Takemura
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Patent number: 7675184Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.Type: GrantFiled: June 19, 2008Date of Patent: March 9, 2010Assignee: Panasonic CorporationInventors: Manabu Ohnishi, Koji Takemura, Noriyuki Nagai, Hoyeun Huh, Tomoyuki Nakayama, Atsushi Doi
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Publication number: 20090200677Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: ApplicationFiled: April 27, 2009Publication date: August 13, 2009Applicant: PANASONIC CORPORATIONInventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Patent number: 7538433Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: GrantFiled: June 15, 2006Date of Patent: May 26, 2009Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Publication number: 20090108410Abstract: A semiconductor device includes a semiconductor substrate, a diffusion layer conductive film formed on the semiconductor substrate, an interlayer insulating film layered on the semiconductor substrate, an interconnect pattern and a via pattern formed in the interlayer insulating film, a plurality of circuit regions formed in the semiconductor substrate, and a scribe region formed around the circuit regions and separating the circuit regions from each other. The diffusion layer conductive film is not formed at least in a region to which laser light is emitted in the scribe region.Type: ApplicationFiled: June 11, 2008Publication date: April 30, 2009Inventors: Koji Takemura, Takahiro Kumakawa, Yoshihiro Matsushima