Patents by Inventor Koji Taniguchi

Koji Taniguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040053061
    Abstract: It is an object of the invention to provide a material for insulating substrate, a printed board, a laminate, copper foil with resin, a copper-clad laminate, a polyimide film, a film for TAB and a prepreg, which are excellent in physical properties, dimensional stability, heat resistance, flame retardancy etc.
    Type: Application
    Filed: October 24, 2003
    Publication date: March 18, 2004
    Inventors: Koji Yonezawa, Koichi Shibayama, Masao Fushimi, Hideyuki Takahashi, Koji Taniguchi, Motohiro Yagi
  • Publication number: 20040046215
    Abstract: In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate 1 near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.
    Type: Application
    Filed: January 11, 1999
    Publication date: March 11, 2004
    Inventors: EIJI HASUNUMA, HIDEKI GENJO, SHIGERU SHIRATAKE, ATSUSHI HACHISUKA, KOJI TANIGUCHI
  • Publication number: 20040039040
    Abstract: Disclosed are novel urea derivatives and their medical uses, especially as adhesion molecule inhibitors useful for therapies of inflammatory diseases.
    Type: Application
    Filed: March 14, 2003
    Publication date: February 26, 2004
    Inventors: Toshiya Takahashi, Takeshi Ishigaki, Miyuki Funahashi, Koji Taniguchi, Masayuki Kaneko, Mie Kainoh, Hiroyuki Meguro
  • Publication number: 20040034627
    Abstract: The present invention creates contents which are structure description data in which a predetermined element and document data associated with this element are written in a structure description language, inputs the element to these contents and extracts the document data corresponding to the input element, and thereby allows the user to extract the document data adapted to the predetermined element from one content.
    Type: Application
    Filed: April 28, 2003
    Publication date: February 19, 2004
    Inventors: Hiroyuki Tada, Koji Taniguchi, Junichi Sato
  • Patent number: 6661700
    Abstract: A semiconductor memory device of the present invention has a memory array structure wherein a plurality of word lines and a plurality of bit lines for selecting a predetermined memory cell are arranged to intersect with one another, and includes two memory cells (e.g., MC1 and MC2) constituting one bit and a sense amplifier electrically connected to the both memory cells through the bit lines. The word line (e.g., WL3A) electrically connected to one (e.g., MC1) of the two memory cells constituting one bit and the word line (e.g., WL3B) electrically connected to the other memory cell (e.g., MC2) are arranged opposite each other across the sense amplifier. Thus, a twin-cell type semiconductor memory device capable of reducing a plane area occupied by a memory cell part while maintaining good retention characteristics.
    Type: Grant
    Filed: April 9, 2002
    Date of Patent: December 9, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Koji Taniguchi
  • Publication number: 20030156391
    Abstract: A circuit board comprising a first solder leading land 13a disposed next to a mounting land located rearmost in a direction the circuit board moving during flow soldering of an electronic component, and a second solder leading land 13b disposed behind the first solder leading land 13a against the direction. The present invention provides a circuit board which can effectively prevent solder bridges caused by excessive solder accumulated around leads and lands located in the rearmost position while the electronic component is flow soldered at narrow pitches as is represented by a case with QFPIC. The circuit board of the present invention is suitable for use of lead-free solder, thus contributes to an environment protection.
    Type: Application
    Filed: February 11, 2003
    Publication date: August 21, 2003
    Inventors: Mitsushisa Nakai, Keiichi Kuriyama, Akihiro Kyogoku, Yoshinao Nakamoto, Koji Taniguchi, Hiroaki Higashi
  • Publication number: 20030116799
    Abstract: A semiconductor device that can prevent short-circuit occurring between capacitor electrodes and a method of manufacturing the semiconductor device are obtained. A semiconductor includes two capacitor electrodes formed spaced from each other and including conductive impurities of the first conductivity type, and an electrode isolation film located between the two capacitor electrodes and formed at the same layer as that of the two capacitor electrodes, while including conductive impurities of the second conductivity type different from the first conductivity type. This allows the two capacitor electrodes to be electrically isolated from each other, without the etching step or the like, by introducing conductive impurities of the second conductivity type into a region that is located between the two capacitor electrodes and is formed at the same layer as that of the capacitor electrodes.
    Type: Application
    Filed: August 23, 2002
    Publication date: June 26, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Koji Taniguchi
  • Publication number: 20030117554
    Abstract: A display device includes a light modulating medium layer, a corner cube array and a reflective electrode layer. The corner cube array is provided on one side of the light modulating medium layer and includes multiple corner cubes as its unit elements. The reflective electrode layer is provided on the corner cube array and includes multiple reflective electrodes that are spaced apart from each other and that are used to apply a voltage to the light modulating medium layer. When the display device is viewed from over the corner cube array, an arrangement pattern of the corner cubes matches an arrangement pattern of the reflective electrodes in at least one direction.
    Type: Application
    Filed: December 26, 2002
    Publication date: June 26, 2003
    Inventors: Yutaka Sawayama, Kiyoshi Minoura, Ichiro Ihara, Koji Taniguchi, Sayuri Fujiwara
  • Publication number: 20030093810
    Abstract: In a video data transmitting method of sending in real-time video data being externally inputted, when encoding video data being inputted as stream data, start and stop of an encoding process is repeated at a predetermined time interval to carry out a data dividing process whereby a plurality of time-continuous video data are generated as partial video data. Also, metadata of partial video data is generated, which is sent, together with the partial video data, in real-time as partial video metadata.
    Type: Application
    Filed: October 29, 2002
    Publication date: May 15, 2003
    Inventor: Koji Taniguchi
  • Patent number: 6559494
    Abstract: In the fabrication of semiconductor devices, and particularly, semiconductor memories, a gate oxide film and a gate electrode are formed on a semiconductor substrate, and a silicon oxide film is formed on the gate electrode. Thereafter, the entire surface is covered with a silicon nitride film and then with an interlayer oxide film. Bit line contacts are formed in source/drain regions each provided between adjacent gate electrodes according to a SAC technique utilizing the silicon nitride film. In the other source/drain region, a hole is made in the silicon nitride film to form a storage node contact.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: May 6, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Koji Taniguchi
  • Patent number: 6534377
    Abstract: Providing a capacitance element which prevents short-circuit between adjacent storage node layers caused by an adhering conductive foreign matter. A method of manufacturing a capacitance element in which a plurality of aperture portions are formed in an insulation layer on a semiconductor substrate and a storage node layer is formed at inner surfaces of the aperture portions, comprising the steps of forming a plurality of aperture portions in an insulation layer from a surface of a silicon oxide film, forming a conductive layer so as to cover the insulation layer and the silicon oxide film, removing the conductive layer on the silicon oxide film so that the conductive layer remaining inside the aperture portions becomes storage node layers, and removing silicon oxide film.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: March 18, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Koji Taniguchi
  • Publication number: 20030016554
    Abstract: A semiconductor memory device of the present invention has a memory array structure wherein a plurality of word lines and a plurality of bit lines for selecting a predetermined memory cell are arranged to intersect with one another, and includes two memory cells (e.g., MC1 and MC2) constituting one bit and a sense amplifier electrically connected to the both memory cells through the bit lines. The word line (e.g., WL3A) electrically connected to one (e.g., MC1) of the two memory cells constituting one bit and the word line (e.g., WL3B) electrically connected to the other memory cell (e.g., MC2) are arranged opposite each other across the sense amplifier. Thus, a twin-cell type semiconductor memory device capable of reducing a plane area occupied by a memory cell part while maintaining good retention characteristics.
    Type: Application
    Filed: April 9, 2002
    Publication date: January 23, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Koji Taniguchi
  • Publication number: 20020199183
    Abstract: A client's terminal 102 carries out the control of data transmission to a server apparatus 101 depending upon a data transmission program involving data transmission control information provided by the server apparatus 101. The server apparatus 101 transmits also a control-information update message to the client's terminal 102. This disperses, in time, the communications to the server apparatus 101. Thus, the server apparatus 101 can be relieved of communication load.
    Type: Application
    Filed: May 8, 2002
    Publication date: December 26, 2002
    Inventor: Koji Taniguchi
  • Patent number: 6445679
    Abstract: A stream communication system has a plurality of nodes and a network to which each node is connected, the node comprises a stream transfer device to which the encoding stream that data attribute information for every data blocks are added, and has a periodicity in the data structure is transferred, at least one node is allocated as a managing node, and the managing node manages at least one monitoring target node and a control target node, the stream transfer device of the control target node comprises stream conversion section for adjusting an amount of the transfer data as the effective transmission rate coincides to the specified transmission rate based on the data priority decided from data attribute information, the stream transfer device of the monitoring target node comprises internal information notification section for notifying the managing node the state of a load of the node, and the stream transfer device of the managing node comprises feedback control section for recalculating the transmission r
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: September 3, 2002
    Assignee: Digital Vision Laboratories Corporation
    Inventors: Koji Taniguchi, Hideaki Tani
  • Patent number: 6424399
    Abstract: A reflection type liquid crystal display apparatus includes: a first substrate having a plurality of reflecting electrodes; a second substrate having a light transmitting electrode; and a liquid crystal layer disposed between the first substrate and the second substrate. The first substrate includes an insulating substrate, a switching device provided on the insulating substrate for supplying a display voltage signal to the reflecting electrode, a drawing-out electrode connected to the switching device and extending under the reflecting electrode, and an insulating resin layer having a contact hole on the drawing-out electrode. The reflecting electrode is provided on the insulating resin layer, corresponding to each pixel, so as to cover the contact hole, and is electrically connected to the drawing-out electrode at the bottom of the contact hole.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: July 23, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasunori Shimada, Hisakazu Nakamura, Koji Taniguchi
  • Publication number: 20020094617
    Abstract: Providing a capacitance element which prevents short-circuit between adjacent storage node layers caused by an adhering conductive foreign matter.
    Type: Application
    Filed: October 16, 2001
    Publication date: July 18, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Koji Taniguchi
  • Publication number: 20020071080
    Abstract: A liquid crystal display apparatus comprises a pair of substrates, and a liquid crystal layer having negative dielectric anisotropy sandwiched by the pair of substrates. Electrodes are provided on each of the pair of substrates, each pixel being defined by an electrode on one of the pair of substrate and a corresponding electrode on the other of the pair of substrates. Each of the electrodes provided on at least one of the pair of substrates has at least first and second tilted surfaces facing directions different from a direction substantially perpendicular to the substrate surface and being adjacent to each other. An insulating film is provided on a liquid crystal molecule side of the electrodes provided on the at least one of the pair of substrates to bury the tilted surfaces of the electrodes to produce a flat surface of the at least one of the pair of substrates.
    Type: Application
    Filed: November 27, 2001
    Publication date: June 13, 2002
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Koji Taniguchi, Noriko Watanabe, Shigeaki Mizushima
  • Publication number: 20020065748
    Abstract: An information receiving terminal notifies an information distribution server of a request for delivery of content. This delivery request specifies a category of the content, a delivery validity period and a character string in a subject header of an e-mail to be delivered. The information distribution server selects the content conforming to the delivery request from information provided by an information provision terminal, includes the content in the e-mail and delivers the e-mail to the information receiving terminal. The information receiving terminal classifies the e-mail received by means of the character string in the subject header of the delivered e-mail and a date and time when the e-mail is received. With this classification, the information receiving terminal presents the e-mail including the requested content to a user without fail and deletes a past-due e-mail having declined value of information automatically.
    Type: Application
    Filed: November 26, 2001
    Publication date: May 30, 2002
    Inventors: Koji Taniguchi, Wataru Fujikawa
  • Publication number: 20020036804
    Abstract: Disclosed is a system and method of data transmission/reception in which picture signals are encoded into image data, the attribute information of the image data is obtained, meta data are generated from the attribute information of the image data. The image data and the meta data are transmitted separately. With this system and method of data transmission/reception, when predetermined conditions are satisfied, i.e. only when a moving body is detected or abnormal data or data including significant information are detected, image data and meta data are transmitted. Therefore, since not all the data are transmitted, the amount of transmitted data is reduced. As a result, the amount of data accumulated in data recipient can be reduced and the load of data analysis operation can be alleviated. In addition, the burden on an operator visually monitoring image data can be eased. Furthermore, inadvertent failure in checking abnormal data or data including significant information can be prevented.
    Type: Application
    Filed: August 3, 2001
    Publication date: March 28, 2002
    Inventors: Koji Taniguchi, Wataru Fujikawa
  • Patent number: 6323560
    Abstract: The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: November 27, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Koichiro Narimatsu, Shigenori Yamashita, Nobuyuki Yoshioka, Shinya Soeda, Atsushi Hachisuka, Koji Taniguchi, Yuki Miyamoto, Takayuki Saito, Ayumi Minamide