Patents by Inventor Kojiro Kameyama

Kojiro Kameyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9466994
    Abstract: A mobile terminal power receiving module 1 which is housed together with a rechargeable battery 3 in a rechargeable battery pack 2 in a mobile terminal such as a smart phone 5, includes a sheet coil 13 in which a coil 12 constituted by conductors is formed on a flexible circuit board 11 as a circuit pattern and a magnetic sheet 14 made of resin in which magnetic powder is dispersed.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: October 11, 2016
    Assignee: NITTO DENKO CORPORATION
    Inventors: Hiroshi Yamazaki, Kojiro Kameyama, Eiji Toyoda, Hajime Sunahara
  • Patent number: 9165898
    Abstract: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a pad electrode formed on a semiconductor substrate through a first insulation layer, and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein the via hole includes a first opening of which a diameter in a portion close to the pad electrode is larger than a diameter in a portion close to the back surface of the semiconductor substrate, and a second opening formed in the first insulation layer and continuing from the first opening, of which a diameter in a portion close to the pad electrode is smaller than a diameter in a portion close to the front surface of the semiconductor substrate.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: October 20, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Kojiro Kameyama, Akira Suzuki, Yoshio Okayama, Mitsuo Umemoto
  • Patent number: 8154129
    Abstract: In a power MOS transistor, for example, a source electrode is formed so as to be commonly connected to a plurality of source regions formed on the front surface. Thus, a current density varies based on in-plane resistance of the source electrode, thereby providing the necessity of increasing the number of wires connecting the sources and a lead. In the invention, an electrode structure includes a copper plating layer 10e formed on a pad electrode 10a by an electrolytic plating method, and a nickel plating layer 10f and a gold plating layer formed so as to cover the upper and side surfaces of the copper plating layer 10e by an electroless plating method.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: April 10, 2012
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Kikuo Okada, Kojiro Kameyama, Takahiro Oikawa
  • Patent number: 7906430
    Abstract: A peeling prevention layer for preventing an insulation film and a protection layer from peeling is formed in corner portions of a semiconductor device. The peeling prevention layer can increase its peeling prevention effect more when formed in a vacant space of the semiconductor device other than the corner portions, for example, between ball-shaped conductive terminals. In a cross section of the semiconductor device, the peeling prevention layer is formed on the insulation film on the back surface of the semiconductor substrate, and the protection layer formed of a solder resist or the like is formed covering the insulation film and the peeling prevention layer. The peeling prevention layer has a lamination structure of a barrier seed layer and a copper layer formed thereon when formed by an electrolytic plating method.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: March 15, 2011
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Mitsuo Umemoto, Kojiro Kameyama, Akira Suzuki
  • Patent number: 7820548
    Abstract: A result of formation of an opening in a semiconductor substrate can be judged without cutting a semiconductor wafer and observing a cross-section of the cut wafer. A semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, an opening formed in the semiconductor substrate to expose the pad electrode, a wiring layer connected with the pad electrode through the opening and a monitoring opening formed in a scribe line to monitor a result of the formation of the opening.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: October 26, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kojiro Kameyama, Akira Suzuki
  • Patent number: 7759247
    Abstract: This invention provides a semiconductor device and a manufacturing method thereof which can minimize deterioration of electric characteristics of the semiconductor device without increasing an etching process. In the semiconductor device of the invention, a pad electrode layer formed of a first barrier layer and an aluminum layer laminated thereon is formed on a top surface of a semiconductor substrate. A supporting substrate is further attached on the top surface of the semiconductor substrate. A second barrier layer is formed on a back surface of the semiconductor substrate and in a via hole formed from the back surface of the semiconductor substrate to the first barrier layer. Furthermore, a re-distribution layer is formed in the via hole so as to completely fill the via hole or so as not to completely fill the via hole. A ball-shaped terminal is formed on the re-distribution layer.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: July 20, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kojiro Kameyama, Akira Suzuki, Yoshio Okayama
  • Patent number: 7670955
    Abstract: The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A semiconductor substrate is etched to form a via hole from a back surface of the semiconductor substrate to a pad electrode. This etching is performed under an etching condition such that an opening diameter of the via hole at its bottom is larger than a width of the pad electrode. Next, a second insulation film is formed on the back surface of the semiconductor substrate including in the via hole 16, exposing the pad electrode at the bottom of the via hole. Next, a penetrating electrode and a wiring layer are formed, being electrically connected with the pad electrode exposed at the bottom of the via hole 16. Furthermore, a protection layer and a conductive terminal are formed. Finally, the semiconductor substrate is cut and separated in semiconductor dies by dicing.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: March 2, 2010
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Kojiro Kameyama, Akira Suzuki, Mitsuo Umemoto
  • Publication number: 20100044839
    Abstract: Provided are a semiconductor device and a method of manufacturing the same. In semiconductor devices of the conventional technologies, the chip size is increased when a breakdown voltage is increased. In the semiconductor device of this invention, an end of a pn junction interface (5) of a collector region (2) and a base region (3) is formed of a mesa groove (6) made of a trench. Thus, the chip size is not increased even when the mesa groove (6) is deeply formed to increase the breakdown voltage.
    Type: Application
    Filed: October 12, 2007
    Publication date: February 25, 2010
    Applicants: Sanyo Electric Co., Ltd., Sanyo Semoconductor Co., Ltd.
    Inventors: Kikuo Okada, Kojiro Kameyama
  • Patent number: 7659576
    Abstract: A punch-through type IGBT generally has a thick p++-type collector layer. Therefore, the FWD need be externally attached to the IGBT when the IGBT is used as a switching element in an inverter circuit for driving a motor load, and thus the number of processes and components increases. In the invention, trenches are formed penetrating through a collector layer and reaching a buffer layer. A collector electrode is formed in the trenches, too. With this structure, a current path is formed between an emitter electrode and the collector electrode without through the collector layer and functions as the FWD.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: February 9, 2010
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Kikuo Okada, Kojiro Kameyama
  • Patent number: 7646100
    Abstract: The first pad electrode layer is disposed on the surface of the semiconductor substrate with the first insulating film between them. Then, the second insulating film with the first via hole partially exposing the first pad electrode layer is formed over the first pad electrode layer. The plug is formed in the first via hole in the next process. The second pad electrode layer connected to the plug is disposed on the second insulating film. Next, the second via hole reaching to the first pad electrode layer from the backside of the semiconductor substrate is formed. The penetrating electrode and the second wiring layer connected to the first pad electrode layer at the bottom part of the second via hole are disposed. Furthermore, the protecting layer and the conductive terminal are formed. Finally, the semiconductor substrate is diced into the semiconductor chips.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: January 12, 2010
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Kojiro Kameyama, Akira Suzuki, Mitsuo Umemoto
  • Publication number: 20090315175
    Abstract: In a power MOS transistor, for example, a source electrode is formed so as to be commonly connected to a plurality of source regions formed on the front surface. Thus, a current density varies based on in-plane resistance of the source electrode, thereby providing the necessity of increasing the number of wires connecting the sources and a lead. In the invention, an electrode structure includes a copper plating layer 10e formed on a pad electrode 10a by an electrolytic plating method, and a nickel plating layer 10f and a gold plating layer formed so as to cover the upper and side surfaces of the copper plating layer 10e by an electroless plating method.
    Type: Application
    Filed: April 4, 2008
    Publication date: December 24, 2009
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Kikuo Okada, Kojiro Kameyama, Takahiro Oikawa
  • Patent number: 7582971
    Abstract: The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A refractory metal layer is formed on a pad electrode formed on a semiconductor substrate with a first insulation film therebetween. Next, a passivation layer is formed on a front surface of the semiconductor substrate including on the pad electrode and on the refractory metal layer, and a supporting body is further formed with a resin layer therebetween. Next the semiconductor substrate is etched to form a via hole from a back surface of the semiconductor substrate to the pad electrode. Next, a penetrating electrode electrically connected with the pad electrode exposed at a bottom of the via hole and a wiring layer 21 are formed with a second insulation film therebetween. Furthermore, a solder resist layer and a conductive terminal are formed.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: September 1, 2009
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductor Co., Ltd.
    Inventors: Kojiro Kameyama, Akira Suzuki, Mitsuo Umemoto
  • Publication number: 20090124078
    Abstract: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a pad electrode formed on a semiconductor substrate through a first insulation layer, and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein the via hole includes a first opening of which a diameter in a portion close to the pad electrode is larger than a diameter in a portion close to the back surface of the semiconductor substrate, and a second opening formed in the first insulation layer and continuing from the first opening, of which a diameter in a portion close to the pad electrode is smaller than a diameter in a portion close to the front surface of the semiconductor substrate.
    Type: Application
    Filed: December 30, 2008
    Publication date: May 14, 2009
    Applicant: SANYO Electric Co., Ltd.
    Inventors: Kojiro KAMEYAMA, Akira SUZUKI, Yoshio OKAYAMA, Mitsuo UMEMOTO
  • Patent number: 7495881
    Abstract: The invention provides an electrostatically chucking technology capable of chucking a workpiece formed of an insulator or a workpiece attached with an object to be processed such as a semiconductor wafer on a stage. A layered body attached with a glass substrate for supporting a semiconductor substrate having an electronic device on its surface is prepared, and a conductive film is attached thereto. Then, the layered body is set on a surface of a stage set in a vacuum chamber such as a dry-etching apparatus. After then, a voltage is applied to an internal electrode to generate positive and negative electric charges on the surfaces of the conductive film and the stage, and the layered body is chucked with static electricity generated therebetween. Then, the layered body chucked on the stage is processed by etching, CVD, or PVD.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: February 24, 2009
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Kojiro Kameyama, Akira Suzuki, Yoshio Okayama, Mitsuo Umemoto
  • Patent number: 7485967
    Abstract: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a pad electrode formed on a semiconductor substrate through a first insulation layer, and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein the via hole includes a first opening of which a diameter in a portion close to the pad electrode is larger than a diameter in a portion close to the back surface of the semiconductor substrate, and a second opening formed in the first insulation layer and continuing from the first opening, of which a diameter in a portion close to the pad electrode is smaller than a diameter in a portion close to the front surface of the semiconductor substrate.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: February 3, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kojiro Kameyama, Akira Suzuki, Yoshio Okayama, Mitsuo Umemoto
  • Publication number: 20080254618
    Abstract: The invention is directed to improvement of reliability of a semiconductor device having penetrating electrodes by preventing a protection film and an insulation film peeling. A peeling prevention layer for preventing an insulation film and a protection layer peeling is formed in corner portions of the semiconductor device. The peeling prevention layer can increase its peeling prevention effect more when formed in a vacant space of the semiconductor device other than the corner portions, for example, between ball-shaped conductive terminals. In a cross section of the semiconductor device, the peeling prevention layer is formed on the insulation film on the back surface of the semiconductor substrate, and the protection layer formed of a solder resist or the like is formed covering the insulation film and the peeling prevention layer. The peeling prevention layer has a lamination structure of a barrier seed layer and a copper layer formed thereon when formed by an electrolytic plating method.
    Type: Application
    Filed: April 25, 2008
    Publication date: October 16, 2008
    Applicants: SANYO ELECTRIC CO., LTD., Kanto SANYO Semiconductors Co., Ltd.
    Inventors: Mitsuo Umemoto, Kojiro Kameyama, Akira Suzuki
  • Publication number: 20080135870
    Abstract: A punch-through type IGBT generally has a thick p++-type collector layer. Therefore, the FWD need be externally attached to the IGBT when the IGBT is used as a switching element in an inverter circuit for driving a motor load, and thus the number of processes and components increases. In the invention, trenches are formed penetrating through a collector layer and reaching a buffer layer. A collector electrode is formed in the trenches, too. With this structure, a current path is formed between an emitter electrode and the collector electrode without through the collector layer and functions as the FWD.
    Type: Application
    Filed: November 1, 2007
    Publication date: June 12, 2008
    Applicants: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Kikuo Okada, Kojiro Kameyama
  • Publication number: 20080132038
    Abstract: The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A semiconductor substrate is etched to form a via hole from a back surface of the semiconductor substrate to a pad electrode. This etching is performed under an etching condition such that an opening diameter of the via hole at its bottom is larger than a width of the pad electrode. Next, a second insulation film is formed on the back surface of the semiconductor substrate including in the via hole 16, exposing the pad electrode at the bottom of the via hole. Next, a penetrating electrode and a wiring layer are formed, being electrically connected with the pad electrode exposed at the bottom of the via hole 16. Furthermore, a protection layer and a conductive terminal are formed. Finally, the semiconductor substrate is cut and separated in semiconductor dies by dicing.
    Type: Application
    Filed: January 3, 2008
    Publication date: June 5, 2008
    Applicants: SANYO ELECTRIC CO., LTD., KANTO SANYO SEMICONDUCTOR CO., LTD.
    Inventors: Kojiro Kameyama, Akira Suzuki, Mitsuo Umemoto
  • Patent number: 7382037
    Abstract: The invention is directed to improvement of reliability of a semiconductor device having penetrating electrodes by preventing a protection film and an insulation film peeling. A peeling prevention layer for preventing an insulation film and a protection layer peeling is formed in corner portions of the semiconductor device. The peeling prevention layer can increase its peeling prevention effect more when formed in a vacant space of the semiconductor device other than the corner portions, for example, between ball-shaped conductive terminals. In a cross section of the semiconductor device, the peeling prevention layer is formed on the insulation film on the back surface of the semiconductor substrate, and the protection layer formed of a solder resist or the like is formed covering the insulation film and the peeling prevention layer. The peeling prevention layer has a lamination structure of a barrier seed layer and a copper layer formed thereon when formed by an electrolytic plating method.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: June 3, 2008
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Mitsuo Umemoto, Kojiro Kameyama, Akira Suzuki
  • Patent number: 7339273
    Abstract: The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A semiconductor substrate is etched to form a via hole from a back surface of the semiconductor substrate to a pad electrode. This etching is performed under an etching condition such that an opening diameter of the via hole at its bottom is larger than a width of the pad electrode. Next, a second insulation film is formed on the back surface of the semiconductor substrate including in the via hole 16, exposing the pad electrode at the bottom of the via hole. Next, a penetrating electrode and a wiring layer are formed, being electrically connected with the pad electrode exposed at the bottom of the via hole 16. Furthermore, a protection layer and a conductive terminal are formed. Finally, the semiconductor substrate is cut and separated in semiconductor dies by dicing.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: March 4, 2008
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Kojiro Kameyama, Akira Suzuki, Mitsuo Umemoto