Patents by Inventor Kojiro Kameyama

Kojiro Kameyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070254471
    Abstract: A result of formation of an opening in a semiconductor substrate can be judged without cutting a semiconductor wafer and observing a cross-section of the cut wafer. A semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, an opening formed in the semiconductor substrate to expose the pad electrode, a wiring layer connected with the pad electrode through the opening and a monitoring opening formed in a scribe line to monitor a result of the formation of the opening.
    Type: Application
    Filed: July 2, 2007
    Publication date: November 1, 2007
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Kojiro Kameyama, Akira Suzuki
  • Patent number: 7256420
    Abstract: A result of formation of an opening in a semiconductor substrate can be judged without cutting a semiconductor wafer and observing a cross-section of the cut wafer. A semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, an opening formed in the semiconductor substrate to expose the pad electrode, a wiring layer connected with the pad electrode through the opening and a monitoring opening formed in a scribe line to monitor a result of the formation of the opening.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: August 14, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kojiro Kameyama, Akira Suzuki
  • Publication number: 20060202348
    Abstract: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a pad electrode formed on a semiconductor substrate through a first insulation layer, and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein the via hole includes a first opening of which a diameter in a portion close to the pad electrode is larger than a diameter in a portion close to the back surface of the semiconductor substrate, and a second opening formed in the first insulation layer and continuing from the first opening, of which a diameter in a portion close to the pad electrode is smaller than a diameter in a portion close to the front surface of the semiconductor substrate.
    Type: Application
    Filed: February 27, 2006
    Publication date: September 14, 2006
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Kojiro Kameyama, Akira Suzuki, Yoshio Okayama, Mitsuo Umemoto
  • Publication number: 20060120010
    Abstract: The invention provides an electrostatically chucking technology capable of chucking a workpiece formed of an insulator or a workpiece attached with an object to be processed such as a semiconductor wafer on a stage. A layered body attached with a glass substrate for supporting a semiconductor substrate having an electronic device on its surface is prepared, and a conductive film is attached thereto. Then, the layered body is set on a surface of a stage set in a vacuum chamber such as a dry-etching apparatus. After then, a voltage is applied to an internal electrode to generate positive and negative electric charges on the surfaces of the conductive film and the stage, and the layered body is chucked with static electricity generated therebetween. Then, the layered body chucked on the stage is processed by etching, CVD, or PVD.
    Type: Application
    Filed: November 28, 2005
    Publication date: June 8, 2006
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Kojiro Kameyama, Akira Suzuki, Yoshio Okayama, Mitsuo Umemoto
  • Publication number: 20060108691
    Abstract: The first pad electrode layer is disposed on the surface of the semiconductor substrate with the first insulating film between them. Then, the second insulating film with the first via hole partially exposing the first pad electrode layer is formed over the first pad electrode layer. The plug is formed in the first via hole in the next process. The second pad electrode layer connected to the plug is disposed on the second insulating film. Next, the second via hole reaching to the first pad electrode layer from the backside of the semiconductor substrate is formed. The penetrating electrode and the second wiring layer connected to the first pad electrode layer at the bottom part of the second via hole are disposed. Furthermore, the protecting layer and the conductive terminal are formed. Finally, the semiconductor substrate is diced into the semiconductor chips.
    Type: Application
    Filed: October 28, 2005
    Publication date: May 25, 2006
    Inventors: Kojiro Kameyama, Akira Suzuki, Mitsuo Umemoto
  • Publication number: 20060108695
    Abstract: The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A semiconductor substrate is etched to form a via hole from a back surface of the semiconductor substrate to a pad electrode. This etching is performed under an etching condition such that an opening diameter of the via hole at its bottom is larger than a width of the pad electrode. Next, a second insulation film is formed on the back surface of the semiconductor substrate including in the via hole 16, exposing the pad electrode at the bottom of the via hole. Next, a penetrating electrode and a wiring layer are formed, being electrically connected with the pad electrode exposed at the bottom of the via hole 16. Furthermore, a protection layer and a conductive terminal are formed. Finally, the semiconductor substrate is cut and separated in semiconductor dies by dicing.
    Type: Application
    Filed: October 25, 2005
    Publication date: May 25, 2006
    Inventors: Kojiro Kameyama, Akira Suzuki, Mitsuo Umemoto
  • Publication number: 20060087042
    Abstract: The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A refractory metal layer is formed on a pad electrode formed on a semiconductor substrate with a first insulation film therebetween. Next, a passivation layer is formed on a front surface of the semiconductor substrate including on the pad electrode and on the refractory metal layer, and a supporting body is further formed with a resin layer therebetween. Next the semiconductor substrate is etched to form a via hole from a back surface of the semiconductor substrate to the pad electrode. Next, a penetrating electrode electrically connected with the pad electrode exposed at a bottom of the via hole and a wiring layer 21 are formed with a second insulation film therebetween. Furthermore, a solder resist layer and a conductive terminal are formed.
    Type: Application
    Filed: October 25, 2005
    Publication date: April 27, 2006
    Inventors: Kojiro Kameyama, Akira Suzuki, Mitsuo Umemoto
  • Publication number: 20060071342
    Abstract: The invention is directed to improvement of reliability of a semiconductor device having penetrating electrodes by preventing a protection film and an insulation film peeling. A peeling prevention layer for preventing an insulation film and a protection layer peeling is formed in corner portions of the semiconductor device. The peeling prevention layer can increase its peeling prevention effect more when formed in a vacant space of the semiconductor device other than the corner portions, for example, between ball-shaped conductive terminals. In a cross section of the semiconductor device, the peeling prevention layer is formed on the insulation film on the back surface of the semiconductor substrate, and the protection layer formed of a solder resist or the like is formed covering the insulation film and the peeling prevention layer. The peeling prevention layer has a lamination structure of a barrier seed layer and a copper layer formed thereon when formed by an electrolytic plating method.
    Type: Application
    Filed: September 28, 2005
    Publication date: April 6, 2006
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Mitsuo Umemoto, Kojiro Kameyama, Akira Suzuki
  • Publication number: 20060073696
    Abstract: A result of formation of an opening in a semiconductor substrate can be judged without cutting a semiconductor wafer and observing a cross-section of the cut wafer. A semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, an opening formed in the semiconductor substrate to expose the pad electrode, a wiring layer connected with the pad electrode through the opening and a monitoring opening formed in a scribe line to monitor a result of the formation of the opening.
    Type: Application
    Filed: September 28, 2005
    Publication date: April 6, 2006
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Kojiro Kameyama, Akira Suzuki