Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a diode region, and a dummy stripe. The substrate has a first surface. The diode region is in the substrate. The diode region includes a first implant region of a first conductivity type approximate to the first surface, and a second implant region of a second conductivity type approximate to the first surface and surrounded by the first implant region. The dummy stripe is on the first surface and located between the first implant region and the second implant region. A method for manufacturing a semiconductor structure is also provided.

Abstract: A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.

Abstract: A semiconductor device includes a transistor. The transistor includes an active region in a substrate, a patterned conductive layer being a portion of an interconnection layer for routing, and an insulating layer extending over the substrate and configured to insulate the active region from the patterned conductive layer. The patterned conductive layer and the insulating layer serve as a gate of the transistor.

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a well region extending in a first direction; a gate electrode disposed within the substrate and overlapping the well region; a gate dielectric layer disposed within the substrate and laterally surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure extending in a second direction different from the first direction over the gate dielectric layer; and an insulating layer extending in the second direction between the second protection structure and the gate dielectric layer.

Abstract: A semiconductor device and a method for forming a semiconductor are provided. The semiconductor device includes: a first substrate, a first conductive line disposed on the first substrate, a second substrate opposite to the first substrate, a second conductive line disposed on the second substrate and adjacent to the first conductive line, and a plurality of bonding structures between the first conductive line and the second conductive line. The first conductive line includes a plurality of first segments separated from one another. The second conductive line includes a plurality of second segments separated from one another. Each of the bonding structures is connected to a respective first segment of the plurality of first segments and a respective second segment of the plurality of second segments such that the plurality of first segments, the plurality of bonding structures and the plurality of second segments are connected in series.

Abstract: A semiconductor structure includes a semiconductor substrate including a first region and a second region; a first device disposed in the first region and a second device disposed in the second region, wherein a voltage level of the first device is greater than a voltage level of the second device; a first isolation disposed in the first region, wherein the first isolation includes a first depth; and a second isolation disposed in the second region, wherein the second isolation includes a second depth, and the first depth is greater than the second depth.

Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage region and a high voltage region are integrated in a substrate. A low voltage transistor device is disposed in the low voltage region and comprises a low voltage gate electrode and a low voltage gate dielectric separating the low voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage gate electrode and the low voltage gate dielectric. A high voltage transistor device is disposed in the high voltage region and comprises a high voltage gate electrode disposed on the first interlayer dielectric layer.

Abstract: A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

Abstract: Some embodiments relate to an integrated circuit (IC) that includes a semiconductor substrate. A shallow trench isolation region downwardly extends into the frontside of the semiconductor substrate and is filled with dielectric material. A first capacitor plate and a second capacitor plate are disposed in the shallow trench isolation region. The first capacitor plate and the second capacitor plate have first and second sidewall structures, respectively, that are substantially parallel to one another and that are separated from one another by the dielectric material of the shallow trench isolation region.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure over a substrate. A metal layer overlies the gate dielectric structure. A conductive layer overlies the metal layer. A polysilicon layer contacts opposing sides of the conductive layer. A bottom surface of the polysilicon layer is aligned with a bottom surface of the conductive layer. A dielectric layer overlies the polysilicon layer. The dielectric layer continuously extends from sidewalls of the polysilicon layer to an upper surface of the conductive layer.

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. A seal-ring structure is arranged in a peripheral region of the 3D IC in the first IC die and the second IC die. The seal-ring structure extends from a first semiconductor substrate of the first IC die to a second semiconductor substrate of the second IC die. A plurality of through silicon via (TSV) coupling structures is arranged at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.

Abstract: A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.

Abstract: A semiconductor structure includes a semiconductor substrate including a first region and a second region; a first device disposed in the first region and a second device disposed in the second region, wherein a voltage level of the first device is greater than a voltage level of the second device; a first isolation disposed in the first region, wherein the first isolation includes a first depth; and a second isolation disposed in the second region, wherein the second isolation includes a second depth, and the first depth is greater than the second depth.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a fully silicided (FUSI) gated device, the method including: forming a masking layer onto a gate structure over a substrate, the gate structure comprising a polysilicon layer. Forming a first source region and a first drain region on opposing sides of the gate structure within the substrate, the gate structure is formed before the first source and drain regions. Performing a first removal process to remove a portion of the masking layer and expose an upper surface of the polysilicon layer. The first source and drain regions are formed before the first removal process. Forming a conductive layer directly contacting the upper surface of the polysilicon layer. The conductive layer is formed after the first removal process. Converting the conductive layer and polysilicon layer into a FUSI layer. The FUSI layer is thin and uniform in thickness.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: A spacer structure and a fabrication method thereof are provided. The method includes the following operations. First and second conductive structures are formed over a substrate. Dielectric layer is formed to cover the first and second conductive structures. Hard mask layer is formed over the dielectric layer. The hard mask layer covers the dielectric layer over the first conductive structure, and the hard mask layer has an opening exposing the dielectric layer over the second conductive structure. The dielectric layer exposed by the hard mask layer is etched to reduce thickness of the dielectric layer. The hard mask layer is removed. The dielectric layer is etched to form first main spacer on sidewall of the first conductive structure and second main spacer on sidewall of the second conductive structure. A first width of the first main spacer is greater than a second width of the second main spacer.