Abstract: A shortest distance between a first p-side electrode and a second p-side connection portion is greater than a shortest distance between the first p-side electrode and a closest one of first n-side connection portions most proximate to the first p-side electrode among a plurality of first n-side connection portions in the plan view. The second p-side electrode is located at least in a region between the first p-side electrode and the closest one of the first n-side connection portions in the plan view.

Abstract: A coherent light source outputs coherent light including high-order harmonics obtained by irradiating short-pulse laser light to a nonlinear medium. A spectrometer includes a grating that diffracts the coherent light and an image sensor that measures an image of the diffracted light. In a first state, a first double slit having a pair of apertures spaced apart in a first direction is arranged at a predetermined position between coherent light source and an incident slit of spectrometer. In a second state, a second double slit that is a replica of first double slit is arranged at the predetermined position as a replacement of first double slit with a sample held in one aperture. A calculation processing device calculates optical constants of the sample based on interference images measured in the first and second states.

Abstract: A moving picture decoding device according to the present invention includes: a determination unit configured to determine the header information and the compressed image data in the stream; a header information storage unit configured to temporarily store the header information determined by the determination unit; a header address storage unit configured to store a header end address indicating an end of header information in a picture, the header end address being an address of the header information storage unit; a compressed image storage unit configured to temporarily store the compressed image data determined by the determination unit; an image address storage unit configured to store an image end address indicating an end of compressed image data in the picture, the image end address being an address of the compressed image storage unit; a header analysis unit configured to analyze the header information for each picture, based on the header end address; and a decoding unit configured to decode the co

Abstract: To provide a multi-pole coaxial connector that can be made more compact. More specifically, to provide a multi-pole coaxial connector in which a pitch between members is reduced to reduce a connecting body in size. In a multi-pole coaxial connector in which when a housing block and a receptacle are coupled to each other, a signal post and a signal contact are brought into conduction, a ground contact and a ground case are brought into conduction, an internal conductor and a signal SMD terminal are brought into conduction, and an external conductor and a ground SMD terminal are brought into conduction, and a cross section of the ground contact is formed into substantially U-shape in which adjacent ground contact side is opened.

Abstract: To provide a multi-pole coaxial connector that can be made more compact. More specifically, to provide a multi-pole coaxial connector in which a pitch between members is reduced to reduce a connecting body in size. In a multi-pole coaxial connector in which when a housing block and a receptacle are coupled to each other, a signal post and a signal contact are brought into conduction, a ground contact and a ground case are brought into conduction, an internal conductor and a signal SMD terminal are brought into conduction, and an external conductor and a ground SMD terminal are brought into conduction, and a cross section of the ground contact is formed into substantially U-shape in which adjacent ground contact side is opened.

Abstract: The present invention provides an image decoding apparatus that realizes speed-up processing of taking out an MR (macroblock remainder) from a fixed length unit that consists of a first DCT block and the MR, without increasing cost. A Setup processor 3 outputs one out of a plurality of fixed length units that constitute an SB (synchronized block). First, calculation is performed for a length from a beginning of the fixed length unit to a EOB (end of block) that is included in the fixed length unit. The calculated length is then used as an offset in taking out the MR. Then an end portion of a second DCT block that is included in the MR is combined with a corresponding beginning portion of the second DCT block, in order to obtain the complete second DCT block. The complete second DCT block is outputted to a variable length code decoder 13.

Abstract: A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.

Abstract: A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing.

Abstract: In a resource request arbitration apparatus according to the present invention, a request masking unit masks a memory access request REQ that is issued by a resource requesting device at over a minimum frequency needed for the resource requesting device, and an arbitrating unit acknowledges one of the memory access requests RREQ that are not suspended by the request masking unit, based on a predetermined static order of priority. With this resource request arbitration apparatus, the arbitrating unit do not have to concern anything other than the predetermined priority order among the memory access requesting units, and an easy and plain arbitration system based on the static priority order ensures the minimum frequency for acknowledging the resource requests that each memory access requesting unit needs.

Abstract: The speed of decoding processing for variable-length coded image data is improved.

Abstract: A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.

Abstract: A decoding apparatus lightens the load incurred by padding processing. When the decoding apparatus outputs decoded data to a frame memory, a padding unit in the decoding apparatus judges whether the decoded data includes boundary pixels, and when boundary pixels are judged to be included, performs padding processing to an extension area using boundary pixel data. As a result, as well as pixels in one decoded macroblock being output, when boundary pixels are included in the output macroblock, the boundary pixels are output to the extension area. This eliminates the need to re-read the boundary pixels from the frame memory.

Abstract: The invention provides a circuit used in a padding and other processes necessary for coding of objects, and performs at high speed pixel processing to generate pixel values to be assigned to cells, using pixel values in a reference area, which includes cells with and without a pixel value. A cell address outputting unit (i) obtains cell addresses indicating positions of a predetermined number of cells serially arranged and binary signals expressing whether those cells each have a pixel value, and (ii) selects, for each cell, two of the obtained cell addresses corresponding to a part of binary signals each expressing that a cell has a pixel value, and outputs the selected cell addresses. A reading unit reads pixel values of the cells at the outputted cell addresses. An operating unit calculates the average of the two read pixel values and outputs the average as a pixel value.

Abstract: A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit 401 for decoding compressed video data to produce frame data, frame memory 402 for storing the frame data, a filtering unit 403 for reducing the frame data in a vertical direction by the vertical filtering to produce a reduced image, buffer memory 404 for storing the reduced image outputted from filtering unit 403, and a control unit 406 for controlling filtering unit 403 based on a decoding state of the video data by decoding unit 401 and a filtering state of the frame data by filtering unit 403, so that overrun and underrun do not occur in filtering unit 403.

Abstract: A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.

Abstract: In a resource request arbitration apparatus according to the present invention, a request masking unit masks a memory access request REQ that is issued by a resource requesting device at over a minimum frequency needed for the resource requesting device, and an arbitrating unit acknowledges one of the memory access requests RREQ that are not suspended by the request masking unit, based on a predetermined static order of priority. With this resource request arbitration apparatus, the arbitrating unit do not have to concern anything other than the predetermined priority order among the memory access requesting units, and an easy and plain arbitration system based on the static priority order ensures the minimum frequency for acknowledging the resource requests that each memory access requesting unit needs.

Abstract: The present invention provides an image decoding apparatus that realizes speed-up processing of taking out an MR (macroblock remainder) from a fixed length unit that consists of a first DCT block and the MR, without increasing cost. A Setup processor 3 outputs one out of a plurality of fixed length units that constitute an SB (synchronized block). First, calculation is performed for a length from a beginning of the fixed length unit to a EOB (end of block) that is included in the fixed length unit. The calculated length is then used as an offset in taking out the MR. Then an end portion of a second DCT block that is included in the MR is combined with a corresponding beginning portion of the second DCT block, in order to obtain the complete second DCT block. The complete second DCT block is outputted to a variable length code decoder 13.

Abstract: A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit 401 for decoding compressed video data to produce frame data, frame memory 402 for storing the frame data, a filtering unit 403 for reducing the frame data in a vertical direction by means of the vertical filtering to produce a reduced image, buffer memory 404 for storing the reduced image outputted from filtering unit 403, and a control unit 406 for controlling filtering unit 403 based on a decoding state of the video data by decoding unit 401 and a filtering state of the frame data by filtering unit 403, so that overrun and underrun do not occur in filtering unit 403.

Abstract: The counter 52 is set with an initial value of “1” and is a counter with a maximum value of “4”. This counter 52 increments the count value held by the flip-flop 51 in synchronization with a clock signal so that the count value changes as shown by the progression 1,2,3,4,1,2,3,4. This clock signal is also used by the instruction decode control unit 11 to control the execution of instructions, with the counting by the counter 52 being performed once for each instruction execution performed by the instruction decode control unit 11. The comparator 54 compares the count value counted by the counter 52 with the maximum value “4”, and when the values match, sets the task switching signal chg_task_ex at a “High” value, so that the processing switches to the execution of the next task.

Abstract: A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.