Patents by Inventor Kosuke Yoshioka

Kosuke Yoshioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6414608
    Abstract: A first bit string extracting unit extracts a first bit string. A first bit length judging unit detects a first codeword from the first bit string. A first decoding unit generates a first run-level pair from the first codeword. A second bit string extracting unit extracts a second bit string. A second bit length judging unit detects a second codeword from the second bit string. A second decoding unit generates a second run-level pair from the second codeword. A first inverse quantizing unit inverse quantizes the first level to obtain a DCT coefficient. A second inverse quantizing unit inverse quantizes the second level to obtain a DCT coefficient. A second buffer controller writes the DCT coefficients and their first buffer addresses into a second buffer. A first buffer controller reads the DCT coefficients and the first buffer addresses from the second buffer and writes the DCT coefficients into a first buffer at the respective first buffer addresses.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: July 2, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideshi Nishida, Kosuke Yoshioka, Tokuzo Kiyohara
  • Publication number: 20020041626
    Abstract: A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing.
    Type: Application
    Filed: October 24, 2001
    Publication date: April 11, 2002
    Inventors: Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara, Kozo Kimura
  • Patent number: 6310921
    Abstract: A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing.
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: October 30, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara, Kozo Kimura
  • Patent number: 6075899
    Abstract: An image memory stores a one-screen image by dividing the one-screen image into a plurality of image blocks which are each m pixels wide by n pixels high. The image memory has an array-like storage region storing s*t first chrominance components that compose one image block and s*t second chrominance components that compose the same image block in serial areas between a start area specified by a row address and a first column address and an end area specified by the same row address and a second column address (see FIG. 10). The storage region also stores m*n luminance components that compose the same image block in serial areas between a different start area specified by a different row address and a third column address and an end area are specified by the different row address and a fourth column address.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: June 13, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara, Kozo Kimura