Abstract: A semiconductor memory device according to an embodiment has a memory cell array including: a plurality of lower wirings extending in the first direction; a plurality of upper wirings extending in the second direction, the upper wirings placed above the plurality of lower wirings; a plurality of memory cells provided at respective crossings of the plurality of lower wirings and the plurality of upper wirings; and an interlayer insulating film provided between the plurality of memory cells adjacent in the second direction, and the device is characterized in that the upper wiring includes: an upper firing first section deposited on the memory cell; and an upper wiring second section deposited on the interlayer insulating film, the upper wiring second section larger in crystal grain size than the upper wiring first section, and an upper surface of the memory cell is lower than an upper surface of the interlayer insulating film.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of interconnects of an nth layer, a plurality of interconnects of a (n+1)th layer, a plurality of stacked films of the nth layer, each of the plurality of stacked films of the nth layer including a memory element, an inter-layer insulating film of the nth layer, a plurality of interconnects of a (n+2)th layer, a plurality of stacked films of the (n+1)th layer, each of the plurality of stacked films of the (n+1)th layer including a memory element, and an inter-layer insulating film of the (n+1)th layer. The inter-layer insulating film of the (n+1)th layer is provided also at a side surface of an end portion in the first direction of the interconnects of the nth layer.

Abstract: A semiconductor storage device according to an embodiment includes a first conductive layer, a variable resistance layer, an electrode layer, a first liner layer, a stopper layer, and a second conductive layer. The first liner layer is configured by a material having a property for canceling an influence of an orientation of a lower layer of the first liner layer, the property of the first liner layer being superior compared with that of the stopper layer. The stopper layer is acted upon by an internal stress in a compressive direction at room temperature.

Abstract: A semiconductor storage device according to an embodiment includes a first conductive layer, a variable resistance layer, an electrode layer, a first liner layer, a stopper layer, and a second conductive layer. The first liner layer is configured by a material having a property for canceling an influence of an orientation of a lower layer of the first liner layer, the property of the first liner layer being superior compared with that of the stopper layer. The stopper layer is acted upon by an internal stress in a compressive direction at room temperature.

Abstract: According to one embodiment, a non-volatile memory device is formed as described below. First, a wiring material layer, which configures a part of a wiring of an element, is stacked above an element layer, the wiring material layer is processed in a predetermined shape, and the element layer is etched using the wiring material layer as a mask. Next, an insulation layer is embedded between etched patterns, and the insulation layer is removed using the wiring material layer as a stopper. Then, a wiring layer, which is in contact with the wiring material layer, is formed on the insulation layer from which the wiring material layer is exposed.

Abstract: According to one embodiment, a non-volatile memory device is formed as described below. First, a wiring material layer, which configures a part of a wiring of an element, is stacked above an element layer, the wiring material layer is processed in a predetermined shape, and the element layer is etched using the wiring material layer as a mask. Next, an insulation layer is embedded between etched patterns, and the insulation layer is removed using the wiring material layer as a stopper. Then, a wiring layer, which is in contact with the wiring material layer, is formed on the insulation layer from which the wiring material layer is exposed.