Abstract: An aluminum oxide film covering a ferroelectric capacitor is formed. Next, an opening (51t) where a portion of a top electrode is exposed and an opening (51b) where a portion of a bottom electrode is exposed are formed in the aluminum oxide film. Thereafter, films (23 to 26) are formed and a resist pattern (92) is formed. Then, etching of the films (23 to 26) is performed with using the resist pattern (92) as a mask thereby forming contact holes (27t) and (27b). At this time, since the openings (51t) and (51b) are formed in the aluminum oxide film, the aluminum oxide film is not required to be processed. Consequently, the contact holes (27t) and (27b) can be formed easily.

Abstract: Provided is a ferroelectric memory including a silicon substrate, a transistor formed on the silicon substrate, and a ferroelectric capacitor formed above the transistor. The ferroelectric capacitor includes a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film, and a metal film formed on the upper electrode.

Abstract: A ferroelectric capacitor is formed above a semiconductor substrate (1), and thereafter, wirings (24a) are formed. A barrier film (25) covering the wirings (24a) is formed. A silicon oxide film (26) embedding gaps between the adjacent wirings (24a) is formed. The silicon oxide film (26) is polished until a surface of the barrier film (25) is exposed by a CMP method. A barrier film (27) is formed on the barrier film (25) and the silicon oxide film (26). Aluminum oxide films are formed as the barrier films (25, 27).

Abstract: A coating solution of SOG is applied on a silicon oxynitride film (11) and precured. As a result, moisture contained in the coating solution volatilizes, and an SOG film (12) is formed. Next, a coating solution of SOG is applied on the SOG film (12) and precured. As a result, an SOG film (13) is formed. Thereafter, a coating solution of SOG is applied on the SOG film (13) and precured. As a result, an SOG film (14) is formed. Subsequently, a main cure of the SOG films (12, 13, and 14) is performed. The viscosity of the coating solution of SOG used for forming the SOG film (12) is lower than those of the coating solutions of SOG used for forming the SOG films (13 and 14).

Abstract: In a manufacturing method of a semiconductor device, a first insulating film covering a ferroelectric capacitor is formed, and a first opening that has a relatively large diameter and reaches an electrode of the ferroelectric capacitor is formed in the first insulating film, and then recovery annealing of the ferroelectric capacitor is performed, and thereby, a path for oxygen can be secured in performing the recovery annealing, and the sufficient recovery annealing can be performed without causing problems during a manufacturing process.

Abstract: A method for manufacturing a semiconductor device including, forming a first insulating film above a silicon substrate, forming an impurity layer in the first insulating film by ion-implanting impurities into a predetermined depth of the first insulating film, and modifying the impurity layer to a barrier insulating film by annealing the first insulating film after the impurity layer is formed, is provided.

Abstract: A ferroelectric capacitor comprising a transistor layer superimposed on a semiconductor substrate, a ferroelectric capacitor layer provided superior to the transistor layer, a wiring layer provided superior to the ferroelectric capacitor layer, and a passivation film. Further, at least one layer of barrier film capable of inhibiting penetration of moisture and hydrogen into the underlayer is provided between the ferroelectric capacitor layer and the passivation film, and the passivation film is characterized by containing a novolac resin.

Abstract: A semiconductor substrate includes a wafer, a first stepped structure formed of plural stepped parts formed on a surface of the wafer with a first area occupation ratio, a second stepped structure formed of plural stepped parts formed on the surface of the wafer with a second, different area occupation ratio, and an interlayer insulation film formed on the surface so as to cover the first and second stepped structures, the interlayer insulation film having a planarized top surface, wherein there are provided at least first and second film-thickness monitoring patterns for monitoring film thickness on the surface in a manner covered by the interlayer insulation film, a first pattern group is formed on the surface such that the first pattern group comprises plural patterns disposed so as to surround the first film-thickness monitoring pattern, a second pattern group is formed on the surface such that the second pattern group comprises plural patterns disposed so as to surround the second film-thickness monitori

Abstract: The semiconductor device according to the present invention comprises: a ferroelectric capacitor 42 formed above a semiconductor substrate 10 and including a lower electrode 36, a ferroelectric film 38 formed on the lower electrode 36 and an upper electrode 40 formed on the ferroelectric film 38; a silicon oxide film 60 formed above the semiconductor substrate 10 and the ferroelectric capacitor 42 and having the surface planarized; a flat barrier film 62 formed on the silicon oxide film 60 with a silicon oxide film 61 formed therebetween, for preventing the diffusion of hydrogen or water; a silicon oxide film 64 formed above the barrier film 62 and having the surface planarized; and a flat barrier film 78 formed on the silicon oxide film 74 with a silicon oxide film 76 formed therebetween, for preventing the diffusion of hydrogen or water.

Abstract: An insulation film (24) having a gradual inclination of a surface is formed by a high density plasma CVD method, an atmospheric pressure CVD method or the like, after a ferroelectric capacitor (23) is formed. Thereafter, an alumina film (25) is formed on the insulation film (24). According to the method, low coverage of the alumina film (25) does not become a problem, and the ferroelectric capacitor (23) is reliably protected.

Abstract: Stable contact hole forming is attained even when an aluminum oxide film is present between layers provided with contact holes. The process comprises the steps of forming a first element layer on a semiconductor substrate; forming a first interlayer insulating film on the first element layer; forming a second element layer on the first interlayer insulating film; forming a second interlayer insulating film on the second element layer; forming a hole resist pattern on the second interlayer insulating film; conducting a first etching for forming of holes by etching the second interlayer insulating film; and conducting a second etching for extending of holes to the first element layer by etching the first interlayer insulating film.

Abstract: Provided is a heat treatment apparatus including a treatment chamber housing a silicon substrate, a heater being provided in the treatment chamber and heating the silicon substrate, and an atmosphere adjustment mechanism reducing a concentration of oxygen contained in an atmosphere inside the treatment chamber to less than an oxygen concentration in the air. The atmosphere adjustment mechanism is provided with an oxygen trap, for example.

Abstract: After a ferroelectric capacitor is formed, an Al wiring (conductive pad) connected to the ferroelectric capacitor is formed. Then, a silicon oxide film and a silicon nitride film are formed around the Al wiring. Thereafter, as a penetration inhibiting film which inhibits penetration of moisture into the silicon oxide film, an Al2O3 film is formed.

Abstract: Provided is a ferroelectric memory including a silicon substrate, a transistor formed on the silicon substrate, and a ferroelectric capacitor formed above the transistor. The ferroelectric capacitor includes a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film, and a metal film formed on the upper electrode.

Abstract: When producing ferroelectric memory devices on a wafer, a memory cell expected to provide the severest degradation of fatigue characteristics is selected from a chip region of the wafer in which the fatigue characteristics are expected to be the poorest, based on the knowledge acquired in advance with regard to the in-plane distribution of the fatigue characteristics on a wafer. The predetermined number of times of rewriting data is guaranteed by conducting fatigue test in the memory cell thus selected for all of the wafers such that, when the result of the fatigue test is good, the entire devices on the wafer are rendered good with regard to the fatigue characteristics.

Abstract: There is provided a method for manufacturing a semiconductor device, including, forming a first insulating film on a semiconductor substrate, forming a capacitor on the first insulating film, forming a second insulating film covering the capacitor, forming a metal wiring on the second insulating film, forming a first capacitor protective insulating film covering the metal wiring and the second insulating film, forming an insulating sidewall on a side of the metal wiring, forming a third insulating film on the insulating sidewall, forming a hole by etching the third insulating film under a condition that an etching rate of the insulating sidewall would be lower than that of the third insulating film, and forming a conductive plug inside the hole.

Abstract: In a circuit area wherein a semiconductor integrated circuit is to be formed, an isolation insulating film is formed on a surface of a semiconductor substrate (11), and, at the same time, five isolation insulating films (12m) extending in one specific direction are formed within a monitor area (1) at a fixed spacing. Then, a gate insulation film and a gate electrode are formed within the circuit area on the semiconductor substrate (11), and, at the same time, five gate insulation films (13m) and five gate electrodes (14m) extending in the same direction as the isolation insulating films (12m) are formed within the monitor area (1) at the same spacing as that of the isolation insulating films (12m).

Abstract: Stable contact hole forming is attained even when an aluminum oxide film is present between layers provided with contact holes. The process comprises the steps of forming a first element layer on a semiconductor substrate; forming a first interlayer insulating film on the first element layer; forming a second element layer on the first interlayer insulating film; forming a second interlayer insulating film on the second element layer; forming a hole resist pattern on the second interlayer insulating film; conducting a first etching for forming of holes by etching the second interlayer insulating film; and conducting a second etching for extending of holes to the first element layer by etching the first interlayer insulating film.

Abstract: A surface profile sensor includes an interlayer insulating film provided with a planarized upper surface formed above a semiconductor substrate, a detection electrode film formed on the interlayer insulating film, an upper insulating film formed on the detection electrode film and the interlayer insulating film and including the surface on which a silicon nitride film is exposed, and a protection insulating film deposited on the upper insulating film and made of a tetrahedral amorphous carbon (ta-C) film including a window formed on the detection electrode film.

Abstract: A method for manufacturing a semiconductor device including a semiconductor substrate having transistors formed thereon, a first interlayer insulating film formed above the semiconductor substrate and the transistors, a ferroelectric capacitor formed above the first interlayer insulating film, a second interlayer insulating film formed above the first interlayer insulating film and the ferroelectric capacitor, a first metal wiring formed on the second interlayer insulating film, and a protection film formed on an upper surface of the wiring but not on a side surface of the wiring.