Patents by Inventor Kouichi Nagai

Kouichi Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method for manufacturing the same
    Patent number: 7932579
    Abstract: A semiconductor device including a capacitor formed over a semiconductor substrate and including a lower electrode, a dielectric film formed over the lower electrode and an upper electrode formed over the dielectric film, an insulation film formed over the semiconductor substrate and the capacitor, and an electrode pad formed over the insulation film and including an alloy film of aluminum and magnesium.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: April 26, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kouichi Nagai, Kaoru Saigoh
  • Semiconductor device and manufacturing method of the same
    Patent number: 7927946
    Abstract: An interlayer insulating film (14) covering a ferroelectric capacitor is formed and a contact hole (19) reaching a top electrode (11a) is formed in the interlayer insulating film (14). An Al wiring (17) connected to the top electrode (11a) via the contact hole (19) is formed on the interlayer insulating film (14). A planar shape of the contact hole (19) is an ellipse.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: April 19, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • SEMICONDUCTOR DEVICE HAVING METAL WIRINGS OF LAMINATED STRUCTURE
    Publication number: 20110086508
    Abstract: A semiconductor device that includes a metal wiring formed on the insulating film and having a main wiring portion laminated with a plurality of metal films and a metal protection film formed at least on the upper surfaces of the main wiring portion and made of a precious metal material.
    Type: Application
    Filed: December 20, 2010
    Publication date: April 14, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hideaki Kikuchi, Kouichi Nagai, Jirou Miura
  • Semiconductor device having a ferroelectric capacitor
    Patent number: 7915054
    Abstract: An ultra-thin semiconductor chip of an FeRAM, which is miniaturized and highly integrated with characteristic degradation of a ferroelectric capacitor suppressed though a thin package structure is applied to the FeRAM is realized. The semiconductor chip is molded up by using a sealing resin with a filler content set at a value in a range of 90 weight % to 93 weight % to produce a package structure.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: March 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kaoru Saigoh, Kouichi Nagai
  • Method for manufacturing semiconductor device including ferroelectric capacitor
    Patent number: 7906349
    Abstract: A method for manufacturing a semiconductor device includes the step of conducting an acceptance/rejection judgment about the semiconductor device. The acceptance/rejection judgment is conducted by using a hysteresis loop that indicates the relationship between the applied voltage and the polarization quantity of the ferroelectric capacitor.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: March 15, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
    Publication number: 20110049675
    Abstract: A semiconductor device includes a capacitor provided above a substrate including electrodes and a ferroelectric film provided therebetween, a pad electrode electrically connected to one of the electrodes of the capacitor, the pad electrode being formed above the substrate, the pad electrode having a recess on a surface of the substrate, a protective film covering a part of the pad electrode other than the recess on the exposed surface, and a hydrogen absorbing film on the protective film and the recess of the pad electrode.
    Type: Application
    Filed: November 8, 2010
    Publication date: March 3, 2011
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Kouichi NAGAI, Kaoru Saigoh
  • Method of manufacturing semiconductor device and thermal annealing apparatus
    Patent number: 7897414
    Abstract: A method of manufacturing a semiconductor device has forming a ferroelectric film over a substrate, placing the substrate having the ferroelectric film in a chamber substantially held in vacuum, introducing oxygen and an inert gas into the chamber, annealing the ferroelectric film in the chamber, and containing oxygen and the inert gas while the chamber is maintained sealed.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: March 1, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • Semiconductor device having metal wirings of laminated structure
    Patent number: 7880302
    Abstract: A semiconductor device that includes a metal wiring formed on the insulating film and having a main wiring portion laminated with a plurality of metal films and a metal protection film formed at least on the upper surfaces of the main wiring portion and made of a precious metal material.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: February 1, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hideaki Kikuchi, Kouichi Nagai, Jirou Miura
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20110012230
    Abstract: An insulation film (24) having a gradual inclination of a surface is formed by a high density plasma CVD method, an atmospheric pressure CVD method or the like, after a ferroelectric capacitor (23) is formed. Thereafter, an alumina film (25) is formed on the insulation film (24). According to the method, low coverage of the alumina film (25) does not become a problem, and the ferroelectric capacitor (23) is reliably protected.
    Type: Application
    Filed: October 1, 2010
    Publication date: January 20, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazutoshi Izumi, Hitoshi Saito, Naoya Sashida, Kaoru Saigoh, Kouichi Nagai
  • FERROELECTRIC MEMORY AND MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD OF FERROELECTRIC CAPACITOR
    Publication number: 20100320519
    Abstract: Provided is a ferroelectric memory including a silicon substrate, a transistor formed on the silicon substrate, and a ferroelectric capacitor formed above the transistor. The ferroelectric capacitor includes a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film, and a metal film formed on the upper electrode.
    Type: Application
    Filed: September 1, 2010
    Publication date: December 23, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Kouichi Nagai
  • Method of manufacturing semiconductor device and semiconductor device
    Patent number: 7829476
    Abstract: A method of manufacturing a semiconductor device has forming a capacitor having electrodes and a ferroelectric film provided therebetween above a substrate, forming a pad electrode electrically connected to one of the electrodes of the capacitor above the substrate, forming a protective film covering the pad electrode over the substrate, forming an opening in the protective film exposing at least a part of the pad electrode, bringing a measurement terminal into contact with the exposed surface of the pad electrode, etching the surface of the pad electrode after the measurement terminal is brought into contact therewith, and forming a hydrogen absorbing film on the protective film and the pad electrode exposed through the opening.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: November 9, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kouichi Nagai, Kaoru Saigoh
  • Semiconductor device and manufacturing method thereof
    Patent number: 7820456
    Abstract: When adopting a stack-type capacitor structure for a ferroelectric capacitor structure (30), an interlayer insulating film (27) is formed between a lower electrode (39) (or a barrier conductive film) and a conductive plug (22) to eliminate an impact of orientation/level difference on a surface of the conductive plug (22) onto the ferroelectric film (40). Differently from a conductive film like the lower electrode (39) or the barrier conductive film, the interlayer insulating film (27) can be formed without inheriting the orientation/level difference from its lower layers by planarizing the surface thereof.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: October 26, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20100267214
    Abstract: According to the method for manufacturing a semiconductor device, a surface of a lower, insulating film (55) is planarized by CMP or the like, and an upper insulating film (56) and a protective metal film (59) are formed on the lower insulating film (55). Accordingly, the upper insulating film (56) and the protective metal film (59) are formed in such a manner they have an excellent coverage and the water/hydrogen blocking capability of the upper insulating film (56) and the protective metal film (59) is maximized.
    Type: Application
    Filed: May 24, 2010
    Publication date: October 21, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Makoto TAKAHASHI, Kouichi NAGAI
  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20100255675
    Abstract: A method for manufacturing a semiconductor device including, forming a first insulating film above a silicon substrate, forming an impurity layer in the first insulating film by ion-implanting impurities into a predetermined depth of the first insulating film, and modifying the impurity layer to a barrier insulating film by annealing the first insulating film after the impurity layer is formed, is provided.
    Type: Application
    Filed: June 21, 2010
    Publication date: October 7, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Hideaki Kikuchi, Kouichi Nagai, Tomoyuki Kikuchi
  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    Publication number: 20100248395
    Abstract: A ferroelectric capacitor provided with a ferroelectric film (10a) is formed above a semiconductor substrate, and thereafter a wiring (17) directly connected to electrodes (9a, 11a) of a ferroelectric capacitor is formed. Then, a silicon oxide film (18) covering the wiring (17) is formed. As the silicon oxide film (18), a film which has processability higher than that of an aluminum oxide film is formed. Besides, a degree of damage that occurs in the ferroelectric capacitor when the insulating film is formed is equal to or less than that when an aluminum oxide film is formed.
    Type: Application
    Filed: June 9, 2010
    Publication date: September 30, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hideaki KIKUCHI, Kouichi NAGAI
  • Semiconductor device
    Patent number: 7800210
    Abstract: It is an aspect of the embodiments discussed herein to provide a semiconductor device including: a substrate; a base on the substrate; an integrated circuit chip on the base; and a ball grid array type package material made of a resin and encapsulating the integrated circuit chip.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: September 21, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • Method for fabricating semiconductor devices
    Patent number: 7776622
    Abstract: A semiconductor device fabrication method that improves the efficiency of semiconductor device production. A plurality of wafer substrates are set and a process for fabricating semiconductor devices each having a ferroelectric capacitor is begun. After ferroelectric layers are formed over the plurality of wafer substrates, the ferroelectric layers formed are damaged. The plurality of wafer substrates are then rearranged and treatment is performed. In each step in which the ferroelectric layers formed may be damaged, the plurality of wafer substrates are rearranged and treatment is performed. As a result, retention characteristic variations among wafer substrates in the same lot are reduced and the productivity of semiconductor devices is improved.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: August 17, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    Publication number: 20100203682
    Abstract: A semiconductor device including a semiconductor device, an integrated circuit chip, a sealing resin encapsulating the integrated circuit chip and an insulating waterproof film covering at least a portion of a surface of said sealing resin and preventing penetration of moisture into the sealing resin.
    Type: Application
    Filed: April 20, 2010
    Publication date: August 12, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Hideaki Kikuchi, Kouichi Nagai
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20100193851
    Abstract: Provided is a semiconductor device including a semiconductor substrate having transistors formed thereon, a first interlayer insulating film formed above the semiconductor substrate and the transistors, a ferroelectric capacitor formed above the first interlayer insulating film, a second interlayer insulating film formed above the first interlayer insulating film and the ferroelectric capacitor, a first metal wiring formed on the second interlayer insulating film, and a protection film formed on an upper surface of the wiring but not on a side surface of the wiring.
    Type: Application
    Filed: April 12, 2010
    Publication date: August 5, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Kouichi Nagai
  • SEMICONDUCTOR DEVICE
    Publication number: 20100197046
    Abstract: A silicide film is formed between a ferroelectric capacitor structure, which is formed by sandwiching a ferroelectric film between a lower electrode and an upper electrode, and a conductive plug (the conductive material constituting the plug is tungsten (W) for example). Here, an example is shown in which a base film of the conductive plug is the silicide film.
    Type: Application
    Filed: April 15, 2010
    Publication date: August 5, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Hideaki Kikuchi, Kouichi Nagai