Abstract: An electrical current sensor device includes a first printed circuit board assembly, a second printed circuit board assembly positioned opposite to the first printed circuit board assembly, and a holder holding the first and second printed circuit board assemblies and providing a passage to allow an electrical conductor to pass through. The first printed circuit board assembly includes a first sensing circuit having a first element pair that includes two magnetoresistive elements with a first pinning direction, the second printed circuit board assembly comprises a second sensing circuit with a second element pair that includes having two magnetoresistive elements with a second pinning direction that is opposite to the first pinning direction, and the first and second pinning directions are perpendicular to a current direction of a current passing through the electrical conductor, the first sensing circuit electrically connects with the second sensing circuit to form a Wheatstone bridge circuit.

Abstract: An electrical current sensor device includes a first printed circuit board assembly, a second printed circuit board assembly positioned opposite to the first printed circuit board assembly, and a holder holding the first and second printed circuit board assemblies and providing a passage to allow an electrical conductor to pass through. The first printed circuit board assembly includes a first sensing circuit having a first element pair that includes two magnetoresistive elements with a first pinning direction, the second printed circuit board assembly comprises a second sensing circuit with a second element pair that includes having two magnetoresistive elements with a second pinning direction that is opposite to the first pinning direction, and the first and second pinning directions are perpendicular to a current direction of a current passing through the electrical conductor, the first sensing circuit electrically connects with the second sensing circuit to form a Wheatstone bridge circuit.

Abstract: A HGA comprises a slider and a suspension with a flexure having a tongue region for supporting the slider. A read/write transducer and a piezoelectric element are formed oppositely. The connecting points of the curve beams and the inner tongue of the tongue region are in mirror positions to a center point of the inner tongue, and the connecting points of each curve beam are located at opposite sides of a center axis of the flexure. The slider has multiple electrical pads electrically connecting with the read/write transducer. The inner tongue has multiple electrical pads. The flexure has multiple inner leads electrically connected with the electrical pads of the inner tongue formed on the curve beams. The structure of the HGA prevents the read/write transducer from damaged and cause the manufacture of the HGA simpler. The present invention also discloses a suspension and a disk drive unit.

Abstract: A HGA comprises a slider and a suspension with a flexure having a tongue region for supporting the slider. A read/write transducer and a piezoelectric element are formed oppositely. The connecting points of the curve beams and the inner tongue of the tongue region are in mirror positions to a center point of the inner tongue, and the connecting points of each curve beam are located at opposite sides of a center axis of the flexure. The slider has multiple electrical pads electrically connecting with the read/write transducer. The inner tongue has multiple electrical pads. The flexure has multiple inner leads electrically connected with the electrical pads of the inner tongue formed on the curve beams. The structure of the HGA prevents the read/write transducer from damaged and cause the manufacture of the HGA simpler. The present invention also discloses a suspension and a disk drive unit.

Abstract: Servo error signal circuitry apparatus and methods are described. The difference between two bottom envelope signals SEbtm and SFbtm is calculated by a subtracter (40) to generate a difference signal (SEbtm?SFbtm). The difference signal (SEbtm?SFbtm) is input as an alignment signal (AL) to an equalizer (42) and as a basic tracking error signal to the positive input terminal of a second subtracter (52). On the other hand, the difference between two top envelope signals SEtop and SFtop is calculated by a third subtracter (48) to generate a difference signal (SEtop?SFtop). The signal K(SEtop?SFtop) obtained by multiplying a coefficient K with the difference signal using a coefficient multiplier (50) is input to the negative input terminal of the second subtracter (52). The difference signal {(SEbtm?SFbtm)?K(SEtop?SFtop)} output from the second subtracter (52) is used as an offset corrected tracking error signal.

Abstract: The present invention offers an optical disk determination circuit that can improve the stability of the operation to detect the peak (pulse signal) of the received light signal, and that can improve the stability of the optical disk determination operation. When determining the type of optical disk corresponding to the depth from the surface of the plane on which a light beam is irradiated to the data recording layer, light is irradiated while varying the focal position of the light beam at a constant velocity in one direction of the depth direction from the surface of the optical disk. The bottom level of the received light signal corresponding to the intensity of this reflected light is clamped at a specified level by the bottom clamp circuit 43. The received light signal with the bottom level clamped is compared with a specified reference voltage Vref by the comparator 45, and the received light signal peak (pulse signal) is detected corresponding to the results of this comparison.

Abstract: A circuit to improve the SN characteristic of a tracking error signal. This tracking error detection circuit is formed as a push-pull system utilizing a quadrant type photo-detector and provided with 4 gain control amplifiers 20, 22, 24, and 26, 4 bottom envelope circuits 28, 30, 32, and 34, a pair of subtracting circuits 36 and 38, adding (subtracting) circuit 40, offset circuit 42, and gain control circuit 44. Bottom envelope circuits 28, 30, 32, and 34 are configured with a capacitor-type peak-hold circuit, for example, whereby bottom envelopes of RF signals SA, SB, SC, and SD given from light receiving areas A, B, C, and D of a photo-detector via gain control amplifiers 20, 22, 24, and 26 are detected, and bottom envelope signals SAbtm, SBbtm, SCbtm, and SDbtm representing the waveforms of the respective bottom envelopes are output.

Abstract: A servo error detector usable in an optical disk system is provided. An envelope detecting unit (24) detects the top envelopes and bottom envelopes of RF signals SA–SH, and top envelope signals SAtop–SHtop and bottom envelope signals SAbtm–SHbtm that represent the top envelope waveforms and bottom envelope waveforms of RF signals output from an optical detector. An analog/digital conversion unit (26) converts analog top envelope signals SAtop–SHtop and bottom envelope signals SAbtm–SHbtm corresponding to all input RF signals SA–SH to digital top envelope signals QAtop–QHtop and bottom envelope signals QAbtm–QHbtm, respectively. A digital operation unit (28) performs digital operation treatment for digital top envelope signals QAtop–QHtop and bottom envelope signals QAbtm–QHbtm to generate various servo error signals.

Abstract: A mark detecting circuit that stably and reliably detects the marks for address information from an optical disk having tracks formed in a spiral shape and having waviness with a fixed period. In the land pre-pit signal extracting portion 12, by means of first bottom envelope circuit 32 with a high tracking speed, first bottom envelope signal Sbtm1 that represents at high sensitivity the bottom envelope of push-pull signal (SA+SB)?(SC+SD) is generated; and, by means of second bottom envelope circuit 34 with a low tracking speed, second bottom envelope signal Sbtm2 that represents at low sensitivity the bottom envelope waveform of push-pull signal (SA+SB)?(SC+SD) is generated. Then, with the signal, obtained by level shift treatment of said second bottom envelope signal Sbtm2 using offset circuit 36, used as threshold signal Sref, first bottom envelope signal Sbtm1 is converted to a binary form. And land pre-pit signal SLPP is extracted from push-pull signal (SA+SB)?(SC+SD).

Abstract: An amplitude variation detection circuit that can reliably detect the mirror portion independently of the type of optical recording medium, as well as a type of information regenerating apparatus that contains said amplitude variation detecting circuit. Voltage division of top envelope signal Ste and bottom-hold signal Sbh of RF signal Srf is performed by voltage divider (16); then, after amplification by gain control amplifier (19) with a gain that corresponds to the type of optical disc (1), a prescribed offset is added by offset circuit (22) to the signal, and the resulting signal is input as mirror detection threshold signal Smt to comparator (24). The high-frequency noise component of bottom envelope signal Sbe of RF signal Srf is removed by low-pass filter (21); after amplification by gain control amplifier (20) with a gain that corresponds to the type of optical disc (1), the signal is input to comparator (24).

Abstract: A mark detecting circuit that stably and reliably detects the marks for address information from an optical disk having tracks formed in a spiral shape and having waviness with a fixed period. In the land pre-pit signal extracting portion 12, by means of first bottom envelope circuit 32 with a high tracking speed, first bottom envelope signal Sbtm1 that represents at high sensitivity the bottom envelope of push-pull signal (SA+SB)−(SC+SD) is generated; and, by means of second bottom envelope circuit 34 with a low tracking speed, second bottom envelope signal Sbtm2 that represents at low sensitivity the bottom envelope waveform of push-pull signal (SA+SB)−(SC+SD) is generated. Then, with the signal, obtained by level shift treatment of said second bottom envelope signal Sbtm2 using offset circuit 36, used as threshold signal Sref, first bottom envelope signal Sbtm1 is converted to a binary form.

Abstract: A circuit to improve the SN characteristic of a tracking error signal. This tracking error detection circuit is formed as a push-pull system utilizing a quadrant type photo-detector and provided with 4 gain control amplifiers 20, 22, 24, and 26, 4 bottom envelope circuits 28, 30, 32, and 34, a pair of subtracting circuits 36 and 38, adding (subtracting) circuit 40, offset circuit 42, and gain control circuit 44. Bottom envelope circuits 28, 30, 32, and 34 are configured with a capacitor-type peak-hold circuit, for example, whereby bottom envelopes of RF signals SA, SB, SC, and SD given from light receiving areas A, B, C, and D of a photo-detector via gain control amplifiers 20, 22, 24, and 26 are detected, and bottom envelope signals SAbtm, SBbtm, SCbtm, and SDbtm representing the waveforms of the respective bottom envelopes are output.

Abstract: A servo error detector usable in an optical disk system is provided. An envelope detecting unit (24) detects the top envelopes and bottom envelopes of RF signals SA−SH, and top envelope signals SAtop−SHtop and bottom envelope signals SAbtm−SHbtm that represent the top envelope waveforms and bottom envelope waveforms of RF signals output from an optical detector. An analog/digital conversion unit (26) converts analog top envelope signals SAtop−SHtop and bottom envelope signals SAbtm−SHbtm corresponding to all input RF signals SA−SH to digital top envelope signals QAtop−QHtop and bottom envelope signals QAbtm−QHbtm, respectively. A digital operation unit (28) performs digital operation treatment for digital top envelope signals QAtop−QHtop and bottom envelope signals QAbtm−QHbtm to generate various servo error signals.

Abstract: A method and apparatus to make the signal slice level during data qualification in an Optical Disc apparatus adaptable to DSV variation. According to this method, phase error signals from a Phase Locked Loop (PLL) subjected to the input data signal are used to generate Pump Up (PU) and Pump Down (PD) signals. These signals are used to determine a direction and degree of a slice level shift and to control a voltage adjustment, by feedback, of the modulated input analog signal to compensate for the slice level shift. The present invention also adapts to the presence of non-zero DSV, or DC components, by generating phase error signals (also by the PLL) when DC components (and corresponding DSV variation) are detected. When DC components are detected, slice level shift is cancelled. In this manner, the method suppresses a system response to any effects of DC component variation and thereby adapts to their presence.

Abstract: An amplitude variation detection circuit that can reliably detect the mirror portion independently of the type of optical recording medium, as well as a type of information regenerating apparatus that contains said amplitude variation detecting circuit. Voltage division of top envelope signal Ste and bottom-hold signal Sbh of RF signal Srf is performed by voltage divider (16); then, after amplification by gain control amplifier (19) with a gain that corresponds to the type of optical disc (1), a prescribed offset is added by offset circuit (22) to the signal, and the resulting signal is input as mirror detection threshold signal Smt to comparator (24). The high-frequency noise component of bottom envelope signal Sbe of RF signal Srf is removed by low-pass filter (21); after amplification by gain control amplifier (20) with a gain that corresponds to the type of optical disc (1), the signal is input to comparator (24).

Abstract: Servo error signal circuitry apparatus and methods are described. The difference between two bottom envelope signals SEbtm and SFbtm is calculated by a subtracter (40) to generate a difference signal (SEbtm−SFbtm). The difference signal (SEbtm−SFbtm) is input as an alignment signal (AL) to an equalizer (42) and as a basic tracking error signal to the positive input terminal of a second subtracter (52). On the other hand, the difference between two top envelope signals SEtop and SFtop is calculated by a third subtracter (48) to generate a difference signal (SEtop−SFtop). The signal K(SEtop−SFtop) obtained by multiplying a coefficient K with the difference signal using a coefficient multiplier (50) is input to the negative input terminal of the second subtracter (52). The difference signal {(SEbtm−SFbtm)−K(SEtop−SFtop)} output from the second subtracter (52) is used as an offset corrected tracking error signal.

Abstract: The present invention offers an optical disk determination circuit that can improve the stability of the operation to detect the peak (pulse signal) of the received light signal, and that can improve the stability of the optical disk determination operation. When determining the type of optical disk corresponding to the depth from the surface of the plane on which a light beam is irradiated to the data recording layer, light is irradiated while varying the focal position of the light beam at a constant velocity in one direction of the depth direction from the surface of the optical disk. The bottom level of the received light signal corresponding to the intensity of this reflected light is clamped at a specified level by the bottom clamp circuit 43. The received light signal with the bottom level clamped is compared with a specified reference voltage Vref by the comparator 45, and the received light signal peak (pulse signal) is detected corresponding to the results of this comparison.

Abstract: Circuitry and method for synchronizing operating speeds of signal processing devices to the data rate of a signal. It applies in particular to Compact Disk (CD) and Digital Versatile Disk (DVD) drives to be used with portable devices. The circuitry does not require clock synchronization speeds in excess of the instantaneous data rate used by the disk drive and also reduces power consumption.

Abstract: The present invention discloses a fully integrated data synchronization circuit for a disk drive read channel system. The data synchronization system comprises dual data synchronizers to provide read reference clocks. Dual PLL circuits are coupled to the data synchronizers to provide a stable reference frequency to data synchronizers. One of the two data synchronizers is used to obtain leading edge data, while the other is for trailing edge data. Each PLL circuit comprises a phase detector, a charge pump, and a VCO. A loop filter is used in conjunction with a charge pump to control loop characteristics of the PLLs. In an idle mode, one of the PLLs is used as a time base generator to provide a stable reference frequency to data synchronizers. Once data synchronizers achieve lock using the stable reference frequency and switch over to read data, the time base generator PLL is switched over to function as a data synchronizer PLL in a read mode.

Abstract: A delay circuit for delaying a digital input signal has a ramp generator, a logic circuit which provides a delayed output when the ramp voltage reaches threshold voltage, and a bias circuit which provides bias voltage to the ramp generator so that the delayed output is free from temperature variation, power supply voltage variation and process variation of semiconductor elements.