Abstract: A test signal generating circuit for generating a test signal for testing logic circuits comprises four delay units each including a setting circuitry for setting a delay time, a gate and a counter for counting clock pulses in number corresponding to the delay time placed in the setting circuitry. The output signals of two delay units are applied to a flip-flop as set input signals, while the output signals of the other two delay units are applied to the flip-flop as reset input signals, whereby the timing and/or waveform of the test signal outputted by the flip-flop is varied in dependence on the values placed in the setting circuitries.

Abstract: A timing signal generating apparatus comprises a first shift register having an input supplied with a first select signal and shifting the first select signal with a first reference clock signal, a second shift register having an input supplied with timing data for shifting the timing data with the first reference clock signal, a first selector having an input supplied with the output of the first shift register and extracting the output from the first shift register at a position corresponding to the stage designated by a second select signal, a second selector having an input supplied with the output of the second shift register for producing the output from the second shift register at a position corresponding to the stage designated by the second select signal, a gate circuit having inputs supplied with a second reference clock signal delayed in phase relative to the first reference clock and the output of the first selector, respectively, a counter for counting a clock signal of a repetition period short