Patents by Inventor Krishna K. Parat
Krishna K. Parat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240127896Abstract: A storage device includes a storage array having multiple decks of NAND cells in a three dimensional (3D) stack. There can be any number of decks that have multiple wordlines in vertical stacks. The decks include a first deck and a second deck. Bias circuitry can apply different voltages to different decks of the storage array. The bias circuitry can apply a low bias to the first deck, with a first voltage low enough to not turn on the NAND cells of the first deck, and simultaneously apply a high bias to the second deck, with a second voltage high enough to turn on the NAND cells of the second deck.Type: ApplicationFiled: December 23, 2023Publication date: April 18, 2024Inventors: Chao ZHANG, Xin SUN, Richard FASTOW, Giuseppina PUZZILLI, Krishna K. PARAT
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Patent number: 11923289Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.Type: GrantFiled: June 10, 2022Date of Patent: March 5, 2024Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Roger W. Lindsay, Krishna K. Parat
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Patent number: 11763889Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.Type: GrantFiled: March 28, 2022Date of Patent: September 19, 2023Assignee: Micron Technology, Inc.Inventors: Benben Li, Akira Goda, Ramey M. Abdelrahaman, Ian C. Laboriante, Krishna K. Parat
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Patent number: 11653494Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.Type: GrantFiled: December 23, 2019Date of Patent: May 16, 2023Assignee: Micron Technology, Inc.Inventors: Fatma Arzum Simsek-Ege, Krishna K. Parat, Luan C. Tran, Meng-Wei Kuo, Yushi Hu
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Publication number: 20220359441Abstract: Three-dimensional (3D) NAND components formed with control circuitry split across two wafers can provide for more area for control circuitry for an array, enabling improved 3D NAND system performance. In one example, a 3D NAND component includes a first die including a three-dimensional (3D) NAND array and first complementary metal oxide semiconductor (CMOS) control circuitry to access the 3D NAND array, and a second die vertically stacked and bonded with the first die, the second die including second CMOS control circuitry to access the 3D NAND array of the first die.Type: ApplicationFiled: May 7, 2021Publication date: November 10, 2022Inventors: Khaled HASNAT, Prashant MAJHI, Owen JUNGROTH, Richard FASTOW, Krishna K. PARAT
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Publication number: 20220302015Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.Type: ApplicationFiled: June 10, 2022Publication date: September 22, 2022Applicant: Micron Technology, Inc.Inventors: Sanh D. Tang, Roger W. Lindsay, Krishna K. Parat
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Publication number: 20220284959Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.Type: ApplicationFiled: March 28, 2022Publication date: September 8, 2022Inventors: Benben Li, Akira Goda, Ramey M. Abdelrahaman, Ian C. Laboriante, Krishna K. Parat
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Patent number: 11393748Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.Type: GrantFiled: April 16, 2020Date of Patent: July 19, 2022Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Roger W. Lindsay, Krishna K. Parat
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Publication number: 20220189552Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.Type: ApplicationFiled: December 23, 2021Publication date: June 16, 2022Inventors: Akira Goda, Shafqat Ahmed, Khaled Hasnat, Krishna K. Parat
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Patent number: 11289163Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.Type: GrantFiled: November 2, 2020Date of Patent: March 29, 2022Assignee: Micron Technology, Inc.Inventors: Benben Li, Akira Goda, Ramey M. Abdelrahaman, Ian C. Laboriante, Krishna K. Parat
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Patent number: 11270778Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.Type: GrantFiled: April 17, 2020Date of Patent: March 8, 2022Assignee: Intel CorporationInventors: Han Zhao, Pranav Kalavade, Krishna K. Parat
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Patent number: 11211126Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.Type: GrantFiled: September 21, 2020Date of Patent: December 28, 2021Assignee: Micron Technology, Inc.Inventors: Akira Goda, Shafqat Ahmed, Khaled Hasnat, Krishna K. Parat
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Patent number: 11043534Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.Type: GrantFiled: January 6, 2020Date of Patent: June 22, 2021Assignee: Micron Technology, Inc.Inventors: Fatma Arzum Simsek-Ege, Krishna K. Parat
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Publication number: 20210174874Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.Type: ApplicationFiled: September 21, 2020Publication date: June 10, 2021Inventors: Akira Goda, Shafqat Ahmed, Khaled Hasnat, Krishna K. Parat
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Publication number: 20210117270Abstract: Error correction coding (ECC) mis-corrected reads, if undetected, result in silent data corruption of a non-volatile memory device. Overcoming ECC mis-corrected reads is based on a read signature of a result of reading a page in the non-volatile memory device. An ECC mis-correct logic counts the number of bits in the end-most buckets into which the bits of the result is divided. End-most buckets that are overpopulated or starved reveal a tell-tale read signature of an ECC mis-correct. The ECC mis-correct is likely to occur when the read reference voltage level used to read the page is shifted in one direction or another to an extreme amount that risks reading data from a different page. Detecting ECC mis-corrected reads can be used to overcome the ECC mis-corrects and mitigate silent data corruption.Type: ApplicationFiled: December 24, 2020Publication date: April 22, 2021Inventors: Krishna K. PARAT, Ravi H. MOTWANI, Rohit S. SHENOY, Ali KHAKIFIROOZ
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Publication number: 20210118508Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.Type: ApplicationFiled: November 2, 2020Publication date: April 22, 2021Inventors: Benben Li, Akira Goda, Ramey M. Abdelrahaman, Ian C. Laboriante, Krishna K. Parat
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Patent number: 10903219Abstract: Flash memory technology is disclosed. In one example, a flash memory cell can include a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure. Associated systems and methods are also disclosed.Type: GrantFiled: May 14, 2019Date of Patent: January 26, 2021Assignee: Intel CorporationInventors: Haitao Liu, Guangyu Huang, Krishna K. Parat, Shrotri B. Kunal, Srikant Jayanti
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Patent number: 10847234Abstract: A technique for read or program verify (PV) operations for non-volatile memory is described. In one example, at the end of a program verify operation (e.g., during a program verify recovery phase), a number of wordlines near a selected wordline are ramped down one at a time. Ramping down wordlines near the selected wordline one at a time can significantly reduce the trapped charge in the channel, enabling lower program disturb rates and improved threshold voltage distributions. In one example, the same technique of ramping down wordlines near the selected wordline can be applied to a read operation.Type: GrantFiled: April 26, 2019Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Han Zhao, Richard Fastow, Krishna K. Parat, Arun Thathachary, Narayanan Ramanan
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Publication number: 20200350028Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.Type: ApplicationFiled: April 17, 2020Publication date: November 5, 2020Applicant: Intel CorporationInventors: HAN ZHAO, PRANAV KALAVADE, KRISHNA K. PARAT
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Patent number: 10825523Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.Type: GrantFiled: October 29, 2019Date of Patent: November 3, 2020Assignee: Micron Technology, Inc.Inventors: Benben Li, Akira Goda, Ramey M. Abdelrahaman, Ian C. Laboriante, Krishna K. Parat