Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

Abstract: Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures.

Abstract: Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a programming pulse to the plurality of memory cells selected for the programming operation after applying a voltage level of a particular step of the multi-step pass voltage to the plurality of memory cells selected for the programming operation, applying a particular voltage level to any data lines coupled to a first subset of memory cells of the plurality of memory cells selected for the programming operation prior to applying a voltage level of a certain step of the multi-step pass voltage, and applying the particular voltage level to any data lines coupled to a second subset of memory cells of the plurality of memory cells selected for the programming operation only after applying the voltage level of the certain step of the multi-step pass voltage.

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

Abstract: An apparatus may include a processor circuit a processor circuit to retrieve data from a non-volatile memory, and a multistrobe read module operable on the processor circuit to set a read operation to read a memory cell over a multiplicity of sense operations, where each sense operation is performed under a different sense condition. The multistrobe read module may be further operable to schedule a new sense operation to succeed a prior sense operation of the multiplicity of sense operations without recharge of the wordline when a value of one or more read condition is within a preset range. Other embodiments are disclosed and claimed.

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

Abstract: Systems, apparatuses and methods may provide for identifying a target sub-block of NAND strings to be partially or wholly erased in memory and triggering a leakage current condition in one or more target select gate drain-side (SGD) devices associated with the target sub-block. Additionally, the leakage current condition may be inhibited in one or more remaining SGD devices associated with remaining sub-blocks of NAND strings in the memory. In one example, triggering the leakage current condition in the one or more target SGD devices includes setting a gate voltage of the one or more target SGD devices to a value that generates a reverse voltage that exceeds a threshold corresponding to the leakage current condition.

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures.