Patents by Inventor Krishna Kalyanasundaram
Krishna Kalyanasundaram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070089540Abstract: A printing platform receives (102) (preferably in-line with a semiconductor device printing process (101)) a substrate having at least one semiconductor device printed thereon and further having a test structure printed thereon, which test structure comprises at least one printed semiconductor layer. These teachings then provide for the automatic testing (103) of the test structure with respect to at least one static (i.e., relatively unchanging) electrical characteristic metric. The static electrical characteristic metric (or metrics) of choice will likely vary with the application setting but can include, for example, a measure of electrical resistance, a measure of electrical reactance, and/or a measure of electrical continuity. Optionally (though preferably) the semiconductor device printing process itself is then adjusted (105) as a function, at least in part, of this metric.Type: ApplicationFiled: October 26, 2005Publication date: April 26, 2007Inventors: Paul Brazis, Daniel Gamota, Krishna Kalyanasundaram, Jie Zhang, Krishna Jonnalagadda
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Publication number: 20070094624Abstract: An apparatus (200) such as a semiconductor device comprises a gate electrode (201) and at least a first electrode (202). The first electrode preferably has an established perimeter that at least partially overlaps with respect to the gate electrode to thereby form a corresponding transistor channel. In a preferred approach the first electrode has a surface area that is reduced notwithstanding the aforementioned established perimeter. This, in turn, aids in reducing any corresponding parasitic capacitance. This reduction in surface area may be accomplished, for example, by providing openings (203) through certain portions of the first electrode.Type: ApplicationFiled: October 26, 2005Publication date: April 26, 2007Inventors: Paul Brazis, Daniel Gamota, Krishna Kalyanasundaram, Jie Zhang
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Publication number: 20070039503Abstract: An energizable design image portion of a provided design pattern (101) is printed (103) on a provided substrate (101) using a functional ink comprised of at least one energy emissive material. A passive design image portion of that design pattern is then also printed (104) on that substrate using at least one graphic arts ink. In a preferred embodiment this process (100) further provides for printing (105) electrically conductive electrodes on the substrate to permit selective energization of the energy emissive material to thereby induce illumination of the energizable design image portion of the design pattern.Type: ApplicationFiled: August 18, 2005Publication date: February 22, 2007Inventors: Tomasz Klosowiak, Krishna Kalyanasundaram, Jie Zhang, Daniel Gamota, Krishna Jonnalagadda
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Publication number: 20060131545Abstract: The density (and hence thickness) of a functional ink layer (41) as comprises a part of an active printed electronic component (71) is determined through interaction (13) of the functional ink with light. This information, in turn, facilitates assessment (14) of the likely corresponding electrical performance of the electronic component. When the functional ink comprises a transparent material, a dye can be added to facilitate the desired interaction and assessment.Type: ApplicationFiled: December 16, 2004Publication date: June 22, 2006Inventors: Krishna Kalyanasundaram, Paul Brazis, Daniel Gamota, Abhijit Chowdhuri, Jie Zhang
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Publication number: 20060121182Abstract: Data regarding printing instructions for an active electronic component are provided (11). These printing instructions will typically comprise instructions regarding the location, geometry, size, orientation, and functional inks used for various component layers as correspond to the electronic component, and are without reference to a specific printing system. This data is then modified (12) as a function of one or more operational proclivities of a particular high throughput additive printing system to provide modified instructions that, when employed to effect the printing of the active electronic component, will improve the resultant yield as compared to the unmodified data.Type: ApplicationFiled: December 3, 2004Publication date: June 8, 2006Inventors: Krishna Kalyanasundaram, Paul Brazis, Daniel Gamota, Jie Zhang
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Publication number: 20050273552Abstract: A method and apparatus for writing to solid-state memory is provided herein. In particular, a controller is provided that monitors operating parameters of each die within the system. In order to enable fast, real-time write operations, feedback from each die is analyzed and compared with a stored set of operating parameters. Based on this comparison, a particular die is chosen for write operations such that system performance is optimized.Type: ApplicationFiled: August 4, 2005Publication date: December 8, 2005Inventors: Paul Brazis, Thomas Tirpak, Kin Tsui, Krishna Kalyanasundaram, Daniel Gamota
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Publication number: 20050189537Abstract: A semiconductor device comprising organic semiconductor material (14) has one or more barrier layers (16) disposed at least partially thereabout to protect the organic semiconductor material (14) from environment-driven changes that typically lead to inoperability of a corresponding device. If desired, the barrier layer can be comprised of partially permeable material that allows some substances therethrough to thereby effect disabling of the encapsulated organic semiconductor device after a substantially predetermined period of time. Getterers (141) may also be used to protect, at least for a period of time, such organic semiconductor material.Type: ApplicationFiled: April 15, 2005Publication date: September 1, 2005Inventors: Steven Scheifers, Daniel Gamota, Andrew Skipor, Krishna Kalyanasundaram
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Publication number: 20050176196Abstract: Organic field effect transistors (OFETs) can be created rapidly and at low cost on organic films by using a multilayer film (202) that has an electrically conducting layer (204, 206) on each side of a dielectric core. The electrically conducting layer is patterned to form gate electrodes (214), and a polymer film (223) is attached onto the gate electrode side of the multilayer dielectric film, using heat and pressure (225) or an adhesive layer (228). A source electrode and a drain electrode (236) are then fashioned on the remaining side of the multilayer dielectric film, and an organic semiconductor (247) is deposited over the source and drain electrodes, so as to fill the gap between the source and drain electrodes and touch a portion of the dielectric film to create an organic field effect transistor.Type: ApplicationFiled: April 8, 2005Publication date: August 11, 2005Inventors: Jie Zhang, Paul Brazis, Daniel Gamota, Krishna Kalyanasundaram, Min-Xian Zhang
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Patent number: 6905908Abstract: Organic field effect transistors (OFETs) can be created rapidly and at low cost on organic films by using a multilayer film (202) that has an electrically conducting layer (204, 206) on each side of a dielectric core. The electrically conducting layer is patterned to form gate electrodes (214), and a polymer film (223) is attached onto the gate electrode side of the multilayer dielectric film, using heat and pressure (225) or an adhesive layer (228). A source electrode and a drain electrode (236) are then fashioned on the remaining side of the multilayer dielectric film, and an organic semiconductor (247) is deposited over the source and drain electrodes, so as to fill the gap between the source and drain electrodes and touch a portion of the dielectric film to create an organic field effect transistor.Type: GrantFiled: December 26, 2002Date of Patent: June 14, 2005Assignee: Motorola, Inc.Inventors: Jie Zhang, Daniel Gamota, Min-Xian Zhang, Paul Brazis, Krishna Kalyanasundaram
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Patent number: 6870181Abstract: An organic field effect transistor utilizes a bifunctional contact-enhancing agent at various interfaces to improve carrier mobility through the organic semiconductor layer, to improve carrier injection, and to enhance adhesion via a bifunctional mechanism. The contact-enhancing agent can be situated between the gate electrode (2) and the dielectric layer (3) to form a chemical or physical bond between the gate electrode and the dielectric layer. It can also be situated between the dielectric layer and the organic semiconducting layer (4), or between the source and drain electrodes (5, 6) and the organic semiconducting layer.Type: GrantFiled: July 2, 2002Date of Patent: March 22, 2005Assignee: Motorola, Inc.Inventors: Jie Zhang, Paul Brazis, Daniel Gamota, Krishna Kalyanasundaram, Steven Scheifers, Jerzy Wielgus, Abhijit Roy Chowdhuri
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Publication number: 20050041453Abstract: A method and apparatus for writing to solid-state memory is provided herein. In particular, a controller is provided that monitors operating parameters of each die within the system. In order to enable fast, real-time write operations, feedback from each die is analyzed and compared with a stored set of operating parameters. Based on this comparison, a particular die is chosen for write operations such that system performance is optimized.Type: ApplicationFiled: August 22, 2003Publication date: February 24, 2005Inventors: Paul Brazis, Thomas Tirpak, Kin Tsui, Krishna Kalyanasundaram, Daniel Gamota
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Publication number: 20040266054Abstract: An exemplary system and method for defining fine printed OFET features is disclosed as comprising inter alia: printed deposition of a conductive material on a substrate; and laser-assisted ablative removal of at least a portion of the conductive material to define source and drain electrode structures. Disclosed features and specifications may be variously controlled, adapted or otherwise optionally modified to improve OFET feature definition. Exemplary embodiments of the present invention representatively provide for resolved OFET channel features that may be readily integrated with or extended to other organic electronic technologies for the improvement of device package form factors, weights and other manufacturing and/or device performance metrics.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Inventors: Paul W. Brazis, Daniel R. Gamota, Krishna Kalyanasundaram, Jie Zhang
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Patent number: 6780733Abstract: A wafer (10) having integrated circuit elements formed therein is thinned and a first carrier (41) is adhered thereto. The first carrier (41) facilitates handling of the thinned wafer (30). A second carrier (51) is then adhered as well and the various integrated circuits are singulated to yield a plurality of thinned die (81). Once the thinned die is mounted to a desired substrate (91), the first carrier (41) is readily removed. In one embodiment, the first carrier (41) has an adhesive that becomes less adherent when exposed to a predetermined stimulus (such as a given temperature range or a given frequency range of photonic energy). Such thinned die (or modules containing such die) are readily amenable to stacking in order to achieve significantly increased circuit densities.Type: GrantFiled: September 6, 2002Date of Patent: August 24, 2004Assignee: Motorola, Inc.Inventors: Marc Chason, Paul Brazis, Krishna Kalyanasundaram, Daniel Gamota
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Publication number: 20040126935Abstract: Organic field effect transistors (OFETs) can be created rapidly and at low cost on organic films by using a multilayer film (202) that has an electrically conducting layer (204, 206) on each side of a dielectric core. The electrically conducting layer is patterned to form gate electrodes (214), and a polymer film (223) is attached onto the gate electrode side of the multilayer dielectric film, using heat and pressure (225) or an adhesive layer (228). A source electrode and a drain electrode (236) are then fashioned on the remaining side of the multilayer dielectric film, and an organic semiconductor (247) is deposited over the source and drain electrodes, so as to fill the gap between the source and drain electrodes and touch a portion of the dielectric film to create an organic field effect transistor.Type: ApplicationFiled: December 26, 2002Publication date: July 1, 2004Inventors: Jie Zhang, Daniel Gamota, Min-Xian Zhang, Paul Brazis, Krishna Kalyanasundaram
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Publication number: 20040048445Abstract: A wafer (10) having integrated circuit elements formed therein is thinned and a first carrier (41) is adhered thereto. The first carrier (41) facilitates handling of the thinned wafer (30). A second carrier (51) is then adhered as well and the various integrated circuits are singulated to yield a plurality of thinned die (81). Once the thinned die is mounted to a desired substrate (91), the first carrier (41) is readily removed. In one embodiment, the first carrier (41) has an adhesive that becomes less adherent when exposed to a predetermined stimulus (such as a given temperature range or a given frequency range of photonic energy). Such thinned die (or modules containing such die) are readily amenable to stacking in order to achieve significantly increased circuit densities.Type: ApplicationFiled: September 6, 2002Publication date: March 11, 2004Applicant: Motorola, Inc.Inventors: Marc Chason, Paul Brazis, Krishna Kalyanasundaram, Daniel Gamota
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Publication number: 20040004213Abstract: An organic field effect transistor utilizes a bifunctional contact-enhancing agent at various interfaces to improve carrier mobility through the organic semiconductor layer, to improve carrier injection, and to enhance adhesion via a bifunctional mechanism. The contact-enhancing agent can be situated between the gate electrode (2) and the dielectric layer (3) to form a chemical or physical bond between the gate electrode and the dielectric layer. It can also be situated between the dielectric layer and the organic semiconducting layer (4), or between the source and drain electrodes (5, 6) and the organic semiconducting layer.Type: ApplicationFiled: July 2, 2002Publication date: January 8, 2004Inventors: Jie Zhang, Paul Brazis, Daniel Gamota, Krishna Kalyanasundaram, Steven Scheifers, Jerzy Wielgus, Abhijit Roy Chowdhuri
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Patent number: 6661024Abstract: An integrated circuit (100, 200, 300, 400) that includes a field effect transistor (102, 202, 302, 402) is fabricated by forming an organic semiconductor channel (112, 216, 308, 418) on one substrate (106, 204), forming device electrodes (114, 116, 110, 208, 210, 212) on one or more other substrates (104, 108, 206), and subsequently laminating the substrates together. In one embodiment, a dielectric patch (214) that functions as a gate dielectric is formed on one of the substrates (204, 206) prior to performing the lamination. Lamination provides a low cost route to device assembly, allows for separate fabrication of different device structures on different substrates, and thins various device layers resulting in improved performance.Type: GrantFiled: July 2, 2002Date of Patent: December 9, 2003Assignee: Motorola, Inc.Inventors: Jie Zhang, Paul Brazis, Daniel Gamota, Krishna Kalyanasundaram, Steven Scheifers, Jerzy Wielgus, Abhijit Roy Chowdhuri
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Publication number: 20030183915Abstract: A semiconductor device comprising organic semiconductor material (14) has one or more barrier layers (16) disposed at least partially thereabout to protect the organic semiconductor material (14) from environment-driven changes that typically lead to inoperability of a corresponding device. If desired, the barrier layer can be comprised of partially permeable material that allows some substances therethrough to thereby effect disabling of the encapsulated organic semiconductor device after a substantially predetermined period of time. Getterers (141) may also be used to protect, at least for a period of time, such organic semiconductor material.Type: ApplicationFiled: April 2, 2002Publication date: October 2, 2003Applicant: Motorola, Inc.Inventors: Steven Scheifers, Daniel Gamota, Andrew Skipor, Krishna Kalyanasundaram