Abstract: Memory cell comprising two conductors, with a serially connected magnetic storage element and a Schottky diode between the two conductors. The Schottky diode provides a unidirectional conductive path between the two conductors and through the element. The Schottky diode is formed between a metal layer in one of the two conductors and a processed junction layer. Methods for process and for operation of the memory cell are also disclosed. The memory cell using the Schottky diode can be designed for high speed operation and with high density of integration. Advantageously, the junction layer can also be used as a hard mask for defining the individual magnetic storage element in the memory cell. The memory cell is particularly useful for magnetic random access memory (MRAM) circuits.

Abstract: In one embodiment of the invention, there is provided a tool for annealing a magnetic stack. The tool includes a housing defining a heating chamber; a holding mechanism to hold at least one wafer in a single line within the heating chamber, a heating mechanism to heat the at least one wafer; and a magnetic field generator to generate a magnetic field whose field lines pass through the single line of wafers during a magnetic annealing process; wherein the holding mechanism comprises a wafer support of holding the single line of wafers between the heating mechanism and the magnetic field generator. The tool may be a rapid thermal processor retrofitted with the magnetic field generator.

Abstract: Embodiments of the invention disclose magnetic memory cell configurations in which a magnetic storage structure is coupled to an upper metal layer with minimal overlay margin. This greatly reduces a size of the memory cell.

Abstract: In one embodiment there is provided, a display driver system, comprising, at least one display driver; a magnetic random access memory (MRAM) macro; and a display driver interface coupling the MRAM macro and the at least one display driver.

Abstract: Magnetic memory cell comprising two conductors and a magnetic storage element between the two conductors, wherein a magnetic enhancement layer (MEL) is provided in the proximity of at least along a partial length of at least one of the two conductors. The MEL is for enhancing a magnetic field in the element when the two conductors are energized. Methods for operation and fabrication process for the memory cell are also disclosed. The memory cell is particularly for use in magnetic random access memory (MRAM) circuits, when using magnetic tunnel junction (MTJ) stacks as the magnetic storage elements.

Abstract: In one embodiment of the invention, there is provided a method for manufacturing a magnetic memory device, comprising: depositing a carbon layer comprising amorphous carbon on a substrate; annealing the carbon layer to activate dopants contained therein; and selectively etching portions of the carbon layer to forms lines of spaced apart carbon conductors.

Abstract: Memory cell comprising two conductors, with a serially connected magnetic storage element and a Schottky diode between the two conductors. The Schottky diode provides a unidirectional conductive path between the two conductors and through the element. The Schottky diode is formed between a metal layer in one of the two conductors and a processed junction layer. Methods for process and for operation of the memory cell are also disclosed. The memory cell using the Schottky diode can be designed for high speed operation and with high density of integration. Advantageously, the junction layer can also be used as a hard mask for defining the individual magnetic storage element in the memory cell. The memory cell is particularly useful for magnetic random access memory (MRAM) circuits.

Abstract: Memory circuit comprising an addressable magnetic tunnel junction (MTJ) stack, forming a magnetic storage element in the circuit. The MTJ stack comprises a tunnel oxide layer between a free layer and a fixed layer. A stress inducing layer is disposed adjacent to the free layer to provide tensile or compressive stress to the free layer, in order to manipulate a magnetic field that is required to write a bit into the MTJ stack. Method of using the memory circuit is also proposed.

Abstract: In one embodiment of the invention, there is provided a method for operating a magnetic memory device. The method comprises selecting a subset of magnetic memory cells of the magnetic memory device; applying a first programming voltage to the selected subset of cells for a predetermined amount of time, wherein the programming voltage is selected to exceed a threshold operating voltage thereby to cause irreversible breakdown of the subset of cells; and reading selected cells of the magnetic memory device by passing a read current through a diode connected in series with each magnetic memory cell.

Abstract: A method for fabricating a circuit, by defining a first set of resist features on a substrate and corresponding to a first mask layout, followed by defining a second set of resist features on the substrate corresponding to a second mask layout, wherein the second set adds to the first set for rectifying an error in either mask layout. In another aspect, the method is by defining a first set of resist features on a substrate and corresponding to a first mask layout that has an error, etching the substrate while the first set protects selected regions, defining a second set of resist features on the substrate and corresponding to a second mask layout, followed by etching the substrate to selectively remove portions of the selected regions for rectifying the error.

Abstract: Memory cell comprising two conductors, with a serially connected magnetic storage element and a Schottky diode between the two conductors. The Schottky diode provides a unidirectional conductive path between the two conductors and through the element. The Schottky diode is formed between a metal layer in one of the two conductors and a processed junction layer. Methods for process and for operation of the memory cell are also disclosed. The memory cell using the Schottky diode can be designed for high speed operation and with high density of integration. Advantageously, the junction layer can also be used as a hard mask for defining the individual magnetic storage element in the memory cell. The memory cell is particularly useful for magnetic random access memory (MRAM) circuits.

Abstract: Disclosed is a memory circuit and method of forming the same. The memory circuit comprises a lower metallization layer defining first conducting lines. A continuous magnetic storage element stack is atop the lower metallization layer wherein a bottom electrode of the stack is in direct contact with the first conducting lines. An upper metallization layer is atop the continuous magnetic storage element stack, the upper metallization layer defining second conducting lines, which are in direct contact with said continuous magnetic storage element stack. Localized areas of the continuous magnetic storage element stack define discrete magnetic bits, each energizable through a selected pair of the first and second conducting lines. In a second aspect and a third aspect, the continuous magnetic storage element stack is respectively partially and fully etched through a single mask, to define the discrete magnetic bits.

Abstract: Disclosed is a memory circuit and method of forming the same. The memory circuit comprises a lower metallization layer defining first conducting lines. A continuous magnetic storage element stack is atop the lower metallization layer wherein a bottom electrode of the stack is in direct contact with the first conducting lines. An upper metallization layer is atop the continuous magnetic storage element stack, the upper metallization layer defining second conducting lines, which are in direct contact with said continuous magnetic storage element stack. Localized areas of the continuous magnetic storage element stack define discrete magnetic bits, each energizable through a selected pair of the first and second conducting lines. In a second aspect and a third aspect, the continuous magnetic storage element stack is respectively partially and fully etched through a single mask, to define the discrete magnetic bits.

Abstract: A method for fabricating a circuit, by defining a first set of resist features on a substrate and corresponding to a first mask layout, followed by defining a second set of resist features on the substrate corresponding to a second mask layout, wherein the second set adds to the first set for rectifying an error in either mask layout. In another aspect, the method is by defining a first set of resist features on a substrate and corresponding to a first mask layout that has an error, etching the substrate while the first set protects selected regions, defining a second set of resist features on the substrate and corresponding to a second mask layout, followed by etching the substrate to selectively remove portions of the selected regions for rectifying the error.

Abstract: A method for fabricating a magnetic film structure is provided. The method comprises forming a magnetic structure on a bottom electrode layer, the magnetic structure comprising at least one pinned bottom magnetic film layer having a fixed magnetic orientation; at least one top magnetic film layer whose magnetic orientation can be manipulated by a current; and a tunneling layer between the bottom magnetic film layer and the top magnetic film layer; forming a metallic hard mask atop the magnetic structure; patterning and etching the metallic hard mask to define exposed areas of the magnetic structure; selectively etching the exposed areas of the magnetic structure by a chemical etch process based on a CO etch chemistry to form discrete magnetic bits.

Abstract: In one embodiment of the invention, there is provided a magnetic random access (MRAM) device. The device comprises a plurality of MRAM cells, wherein each MRAM cell comprises a magnetic bit, and write conductors defined by conductors patterned in a second metal layer above the magnetic bit; and a gate formed below the magnetic bit between a source and a drain; and addressing circuits to address the MRAM cells.

Abstract: Memory circuit comprising an addressable magnetic tunnel junction (MTJ) stack, forming a magnetic storage element in the circuit. The MTJ stack comprises a tunnel oxide layer between a free layer and a fixed layer. A stress inducing layer is disposed adjacent to the free layer to provide tensile or compressive stress to the free layer, in order to manipulate a magnetic field that is required to write a bit into the MTJ stack. Method of using the memory circuit is also proposed.

Abstract: In one embodiment of the invention, there is provided a method for operating a magnetic memory device. The method comprises selecting a subset of magnetic memory cells of the magnetic memory device; applying a first programming voltage to the selected subset of cells for a predetermined amount of time, wherein the programming voltage is selected to exceed a threshold operating voltage thereby to cause irreversible breakdown of the subset of cells; and reading selected cells of the magnetic memory device by passing a read current through a diode connected in series with each magnetic memory cell.

Abstract: In one embodiment of the invention, there is provided a magnetic random access (MRAM) device. The device comprises a plurality of MRAM cells, wherein each MRAM cell comprises a magnetic bit, and write conductors defined by conductors patterned in a second metal layer above the magnetic bit; and a gate formed below the magnetic bit between a source and a drain; and addressing circuits to address the MRAM cells.

Abstract: Disclosed is a memory circuit and method of forming the same. The memory circuit comprises a lower metallization layer defining first conducting lines. A continuous magnetic storage element stack is atop the lower metallization layer wherein a bottom electrode of the stack is in direct contact with the first conducting lines. An upper metallization layer is atop the continuous magnetic storage element stack, the upper metallization layer defining second conducting lines, which are in direct contact with said continuous magnetic storage element stack. Localized areas of the continuous magnetic storage element stack define discrete magnetic bits, each energizable through a selected pair of the first and second conducting lines. In a second aspect and a third aspect, the continuous magnetic storage element stack is respectively partially and fully etched through a single mask, to define the discrete magnetic bits.