SELF CONTACTING BIT LINE TO MRAM CELL
Embodiments of the invention disclose magnetic memory cell configurations in which a magnetic storage structure is coupled to an upper metal layer with minimal overlay margin. This greatly reduces a size of the memory cell.
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This application claims the benefit of priority to U.S. Provisional Patent Application No. 61/473,921 titled “Self-Contacting Bit Line to MRAM cell” filed Apr. 11 2011.
FIELDEmbodiments of the invention relate to MRAM (Magnetic Random Access Memory) semiconductor devices.
BACKGROUNDMRAM (Magnetic Random Access Memory) cells may be fabricated during BEOL (Back End Of Line) after a MOS FET device process. The minimum feature size of an MRAM cell is often 1.5× larger than that of FEOL (Front End of Line). It is therefore difficult to shrink memory size compared with other FEOL based memories.
SUMMARYEmbodiments of the invention disclose a plurality of self-aligned structures that save the overlay margin.
The first embodiment discloses a MTJ cell wherein the MTJ stack is directly coupled to the upper metal without the requirement of a via. Sidewalls of individual MTJ elements are protected with dielectric film spacer to prevent from PIN-Switch layer shorting 10 through the tunnel oxide layer. The top layer of MTJ is exposed to upper metal. Overlay margin in this embodiment is required only for upper metal coverage over MTJ. The upper metal width comes to f+2∂, saving 2∂ compared to previous art. Putting MTJ feature size equal to that of FEOL, the memory size becomes competitive to FEOL based memory.
The second embodiment comprises an electrically conductive material such as Titanium Nitride, which is used as a hard mask. The hard mask is for MTJ stack etch and remains on top of MTJ pillar after the etching. Inter layer oxide is deposited over the MTJ pillar. The hard mask remained on MTJ is exposed with CMP. Metal like as Al/Cu is deposited and patterned with conventional lithography and Reactive Ion Etching. The same reduction in memory cell size as the first embodiment is provided by the second embodiment.
The third embodiment discloses a self-aligned via which replaces the hard mask. Silicon nitride is used as hard mask as an example. The hard mask is for MTJ stack etch and remains on top of MTJ pillar after the etching. Inter layer oxide is deposited over the MTJ pillar. The hard mask remained on MTJ is exposed with CMP or Dual Damascene oxide trench etch. The exposed hard mask is removed by hot phosphoric acid followed by upper metal deposition. The same squeezing memory cell size as the first embodiment is expected on the structure.
The fourth embodiment is of self-aligned etching. MTJ is to be etched twice along word line direction first and bit line direction 2nd. Putting dielectric film, nitride preferred, spacer on MTJ pillar to prevent PIN layer—Fix layer short. Oxide is deposited and planerized by CMP. The oxide is recessed until MTJ appeared. Upper metal layer is deposited patterned. MTJ and bottom read lead is etched with the same mask as upper metal. The upper metal is wrapping around MTJ pillar. It works to help induce magnetic field. The upper metal width can be same size as MTJ pillar. It saves 4∂ compared with prior arts.
The fifth embodiment is also of self-aligned patterning. It is different in read electrode connecting to top of MTJ instead of bottom of the pillar. MTJ is connected to lower metal (write word line). Top metal is electrically isolated from MTJ with a thin dielectric film. The upper metal also wraps around MTJ. It enhances magnetic field induction for switching. It saves cell footprint also by 4∂.
While the appended claims set forth the features of the present invention with particularity, the invention, together with its objects and advantages, will be more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings, wherein:
FIG. A illustrates a cross-sectional view of prior arts.
FIG. B illustrates a top view of prior arts.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form only in order to avoid obscuring the invention.
Reference in this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearance of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments.
Moreover, although the following description contains many specifics for the purposes of illustration, anyone skilled in the art will appreciate that many variations and/or alterations to said details are within the scope of the present invention. Similarly, although many of the features of the present invention are described in terms of each other, or in conjunction with each other, one skilled in the art will appreciate that many of these features can be provided independently of other features. Accordingly, this description of the invention is set forth without any loss of generality to, and without imposing limitations upon, the invention.
Prior Art FIG. A shows a cross-sectional view through a prior art MRAM cell, whereas Prior Art FIG. B shows a plan view of the MRAM cell. As can be seen the MRAM cell includes a MTJ (Magnetic Tunnel Junction) as a memory element. The MTJ is connected to upper and lower metals through via holes where overlay margin ∂ is required on the both edges of via hole landing area. The MTJ cell is designed to be bigger than the upper through hole to upper metal by 2∂. Since the upper metal should cover the MTJ, the upper metal becomes bigger than the MTJ by 2∂. The upper metal width consequently becomes 4∂ bigger than a feature size f of the via hole. Overlay margin is estimated to be 20% to 30% of the minimum 1−b. As will be seen, the upper metal 113 is directly connected feature size. The metal width would be twice bigger than minimum feature size.
As shown in
A cross sectional view of the 2nd embodiment is shown in
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A cross-sectional view of the 3rd embodiment is shown in
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A cross-sectional view of the 4th embodiment is shown in
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A cross-sectional view of the 5th embodiment is shown in
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Tungsten is deposited and allows CMP to make the surface smooth. MTJ Pin layer 505, tunnel oxide 506, MTJ fixed layer 507 and hard mask layer are subsequently deposited as previous embodiments. The stack is patterned as a line along the word line direction and followed by spacer oxide protect the MTJ sidewall as shown in
Although the present invention has been described with reference to specific exemplary embodiments, it will be evident that the various modification and changes can be made to these embodiments without departing from the broader spirit of the invention. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than in a restrictive sense.
Claims
1. A magnetic memory cell, comprising:
- a memory element; and
- an upper metal layer; wherein the memory element is directly coupled to the upper metal layer without the use of a via.
2. The magnetic memory cell of claim 1, wherein the memory element comprises a Magnetic Tunnel Junction (MTJ) stack.
3. The magnetic memory cell of claim 2, wherein a size of the MTJ stack is f and a width of the upper metal layer is f+2∂, where ∂ is an overlay margin for the upper metal layer.
4. The magnetic memory cell of claim 2, further comprising dielectric sidewalls formed on opposed sides of the MTJ stack.
5. The magnetic memory cell of claim 1, further comprising: a hard mask layer etched and patterned to sit atop the memory element.
6. The magnetic memory cell of claim 5, wherein the memory element comprises a Magnetic Tunnel Junction (MTJ) stack.
7. The magnetic memory cell of claim 5, wherein a size of the MTJ stack is f and a width of the upper metal layer is f+2∂, where ∂ is an overlay margin for the upper metal layer.
8. The magnetic memory cell of claim 5, wherein the hard mask layer comprises a material selected from the group consisting of titanium nitride, titanium, aluminum, and tantalum.
9-11. (canceled)
12. A magnetic memory cell, comprising:
- a magnetic memory element;
- a read lead directly coupled to a lower end of the magnetic memory element;
- a bit line directly coupled to an upper end of the magnetic memory element; and
- a word line positioned under the magnetic memory element such that the read lead passes between the word line and the magnetic memory element.
13. The magnetic memory cell of claim 12, wherein a size of the magnetic storage element is f and a width of the bit line is f+2∂, where ∂ is an overlay margin for the bit line.
14. The magnetic memory cell of claim 12, wherein the magnetic memory element comprises a Magnetic Tunnel Junction (MTJ) stack.
15. The magnetic memory cell of claim 13, further comprising dielectric sidewalls formed on sides of the MTJ stack.
16. The magnetic memory cell of claim 12, further comprising a hard mask layer etched and patterned to sit atop the memory element.
17. A magnetic memory cell, comprising:
- a Magnetic Tunnel Junction (MTJ) stack including a plurality of layers;
- a read lead directly coupled to a lower layer of the MTJ stack;
- a bit line directly coupled to an upper layer of the MTJ stack; and
- a word line positioned under the MTJ stack such that the read lead passes between the word line and the MTJ stack.
18. The magnetic memory cell of claim 17, wherein a size of the MTJ stack is f and a width of the bit line is f+2∂, where ∂ is an overlay margin for the bit line.
19. The magnetic memory cell of claim 17, wherein the plurality of layers of the MTJ stack comprises a pin layer, a tunnel oxide layer, and a fixed layer.
20. The magnetic memory cell of claim 17, further comprising dielectric sidewalls formed on sides of the MTJ stack.
21. The magnetic memory cell of claim 17, further comprising a hard mask layer etched and patterned to sit atop the MTJ stack.
22. The magnetic memory cell of claim 21, wherein a size of the MTJ stack is f and a width of the upper metal layer is f+2∂, where ∂ is an overlay margin for the upper metal layer.
23. The magnetic memory cell of claim 21, wherein the hard mask layer comprises a material selected from the group consisting of titanium nitride, titanium, aluminum, and tantalum.
Type: Application
Filed: Apr 11, 2012
Publication Date: Jan 22, 2015
Applicant: MAGSIL CORPORATION (Santa Clara, CA)
Inventor: Krishnakumar Mani (San Jose, CA)
Application Number: 13/444,805
International Classification: H01L 43/02 (20060101);