Abstract: Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: an adhesion layer; a plated barrier layer; and a plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy.

Abstract: A multi-layer pillar is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.

Abstract: Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer.

Abstract: Disclosed are embodiments of an electroplating system and an associated electroplating method that allow for depositing of metal alloys with a uniform plate thickness and with the means to alter dynamically the alloy composition. Specifically, by using multiple anodes, each with different types of soluble metals, the system and method avoid the need for periodic plating bath replacement and also allow the ratio of metals within the deposited alloy to be selectively varied by applying different voltages to the different metals. The system and method further avoids the uneven current density and potential distribution and, thus, the non-uniform plating thicknesses exhibited by prior art methods by selectively varying the shape and placement of the anodes within the plating bath. Additionally, the system and method allows for fine tuning of the plating thickness by using electrically insulating selectively placed prescribed baffles.

Abstract: Semiconductor structures, methods of manufacture and design structures are provided. The structure includes at least one offset crescent shaped solder via formed in contact with an underlying metal pad of a chip. The at least one offset crescent shaped via is offset with respect to at least one of the underlying metal pad and an underlying metal layer in direct electrical contact with an interconnect of the chip which is in electrical contact with the underlying metal layer.

Abstract: Disclosed are embodiments of an electroplating system and an associated electroplating method that allow for depositing of metal alloys with a uniform plate thickness and with the means to alter dynamically the alloy composition. Specifically, by using multiple anodes, each with different types of soluble metals, the system and method avoid the need for periodic plating bath replacement and also allow the ratio of metals within the deposited alloy to be selectively varied by applying different voltages to the different metals. The system and method further avoids the uneven current density and potential distribution and, thus, the non-uniform plating thicknesses exhibited by prior art methods by selectively varying the shape and placement of the anodes within the plating bath. Additionally, the system and method allows for fine tuning of the plating thickness by using electrically insulating selectively placed prescribed baffles.

Abstract: A method of coupling an integrated circuit to a substrate includes providing the substrate, forming a contact pad in the substrate, contacting the contact pad with a solder ball, and repeatedly exposing the solder ball to a thermal process to cause intermetallics based on a metal in the contact pad to be formed in the thermal ball.

Abstract: A chemical etchant containing hydrogen peroxide and phosphate ions at a controlled pH is provided for selectively etching metals in the presence of one or more metals not to be etched. The etchant is useful in the fabrication of semiconductor components particularly for forming capture pads where TiW is used as a barrier layer for a copper, copper/nickel pad, or copper/nickel alloy pad. A commercial hydrogen peroxide solution is preferred to which has been added phosphoric acid as a source of phosphate ions and KOH as the pH adjuster.

Abstract: Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.

Abstract: Disclosed is a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. In a further embodiment, there may also be an aluminum layer between the insulation layer and copper plug. Also disclosed is a process for making the semiconductor device.

Abstract: A method is provided for the removal of tin or tin alloys from substrates such as the removal of residual tin solder from the molds used in the making of interconnect solder bumps on a wafer or other electronic device. The method is particularly useful for the well-known C4NP interconnect technology and uses an etchant composition comprising cupric ions and HCl. Cupric chloride and cupric sulfate are preferred. A preferred method regenerates cupric ions by bubbling air or oxygen through the etchant solution during the cleaning process.

Abstract: Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: an adhesion layer; a plated barrier layer; and a plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy.

Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.

Abstract: An electroless Cu layer is formed on each side of a packaging substrate containing a core, at least one front metal interconnect layer, and at least one backside metal interconnect layer. A photoresist is applied on both electroless Cu layers and lithographically patterned. First electrolytic Cu portions are formed on exposed surfaces of the electroless Cu layers, followed by formation of electrolytic Ni portions and second electrolytic Cu portions. The electrolytic Ni portions provide enhanced resistance to electromigration, while the second electrolytic Cu portions provide an adhesion layer for a solder mask and serves as an oxidation protection layer. Some of the first electrolytic Cu may be masked by lithographic means to block formation of electrolytic Ni portions and second electrolytic Cu portions thereupon as needed. Optionally, the electrolytic Ni portions may be formed directly on electroless Cu layers.

Abstract: A method is provided for the removal of tin or tin alloys from substrates such as the removal of residual tin solder from the molds used in the making of interconnect solder bumps on a wafer or other electronic device. The method is particularly useful for the well-known C4NP interconnect technology and uses an etchant composition comprising cupric ions and HCl. Cupric chloride and cupric sulfate are preferred. A preferred method regenerates cupric ions by bubbling air or oxygen through the etchant solution during the cleaning process.

Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.

Abstract: A chemical etchant containing hydrogen peroxide and phosphate ions at a controlled pH is provided for selectively etching metals in the presence of one or more metals not to be etched. The etchant is useful in the fabrication of semiconductor components particularly for forming capture pads where TiW is used as a barrier layer for a copper, copper/nickel pad, or copper/nickel alloy pad. A commercial hydrogen peroxide solution is preferred to which has been added phosphoric acid as a source of phosphate ions and KOH as the pH adjuster.

Abstract: Disclosed are embodiments of an electroplating system and an associated electroplating method that allow for depositing of metal alloys with a uniform plate thickness and with the means to alter dynamically the alloy composition. Specifically, by using multiple anodes, each with different types of soluble metals, the system and method avoid the need for periodic plating bath replacement and also allow the ratio of metals within the deposited alloy to be selectively varied by applying different voltages to the different metals. The system and method further avoids the uneven current density and potential distribution and, thus, the non-uniform plating thicknesses exhibited by prior art methods by selectively varying the shape and placement of the anodes within the plating bath. Additionally, the system and method allows for fine tuning of the plating thickness by using electrically insulating selectively placed prescribed baffles.

Abstract: A method of producing a metal-graphite foam composite, and particularly, the utilization thereof in connection with a cooling apparatus. Also provided is a cooling apparatus, such as a liquid cooler or alternatively, a heat sink for electronic heat-generating components, which employ the metal-graphite foam composite.

Abstract: A solution for wet etching a copper film within a ball limiting metallurgy (BLM) of a semiconductor device includes, in an exemplary embodiment, an ammonium persulfate etching agent, a potassium sulfate passivation agent for protecting a PbSn solder material, and a pH modifier for controlling the etch rate of the copper film.