Abstract: An epitaxial structure includes a first type semiconductor layer, a light emitting layer, a second type semiconductor layer, and a buffer layer structure. The light emitting layer is disposed on the first type semiconductor layer. The second type semiconductor layer is disposed on the light emitting layer. The buffer layer structure is disposed on one side of the first type semiconductor layer away from the second type semiconductor layer and includes a first buffer layer and a second buffer layer. The second buffer layer is located between the first buffer layer and the first type semiconductor layer, and the first buffer layer has a chlorine concentration greater than a chlorine concentration of the second buffer layer.

Abstract: An ultra-reliable and low latency communications local breakout (URLLC-LBO) method and a URLLC-LBO method for a next generation radio access network (NG-RAN) are provided. The method includes: configuring a core network to establish a packet data unit (PDU) session between first user equipment (UE) and the core network; configuring the first UE to establish a URLLC service; configuring a near real-time RAN intelligent controller (near-RT RIC) to establish an F1-LBO routing process to set an LBO dedicated radio bearer (DRB) for the local URLLC service; configuring an F1-LBO virtual network function (VNF) module according to a traffic rule by the F1-LBO routing process, to establish a routing table through the F1-LBO VNF module, in which the routing table defines a relationship between a first location and a second location of the LBO DRB.

Abstract: A micro light-emitting diode includes a first stacked layer, a second stacked layer, a third stacked layer, a bonding layer, at least one etch stop layer, and a plurality of electrodes. The second stacked layer is disposed between the first stacked layer and the third stacked layer. The first stacked layer includes a first active layer. The second stacked layer includes a second active layer. The third stacked layer includes a third active layer. The bonding layer is disposed between the second stacked layer and the third stacked layer. The at least one etch stop layer is at least disposed between the first active layer and the second active layer. The plurality of electrodes are respectively electrically connected with the first stacked layer, the second stacked layer, and the third stacked layer. At least one electrode of the plurality of electrodes contacts the etch stop layer.

Abstract: A method of descumming a dielectric layer is provided. In an embodiment the dielectric layer is deposited over a substrate, and a photoresist is applied, exposed, and developed after the photoresist has been applied. Once the pattern of the photoresist is transferred to the underlying dielectric layer, a descumming process is performed, wherein the descumming process utilizes a mixture of a carbon-containing precursor, a descumming precursor, and a carrier gas. The mixture is ignited into a treatment plasma, and the treatment plasma is applied to the dielectric layer in order to descum the dielectric layer.

Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

Abstract: An epitaxial structure includes a quantum well structure, a first type semiconductor layer, and a second type semiconductor layer. The quantum well structure has an upper surface and a lower surface opposite to each other and includes at least one quantum well layer and at least one quantum barrier layer stacked alternately. The quantum well layer includes at least one patterned layer, and the patterned layer includes multiple geometric patterns. The first type semiconductor layer is disposed on the lower surface of the quantum well structure. The second type semiconductor layer is disposed on the upper surface of the quantum well structure.

Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

Abstract: A micro light-emitting device includes an epitaxial structure. The epitaxial structure has a bottom surface and includes a plurality of grooves, and the grooves are located on the bottom surface. Each of the grooves includes a plurality of sub-grooves, and the sub-grooves define an inner wall of each of the grooves. A ratio of a size of each of the grooves to a size of each of the sub-grooves is greater than 1 and less than or equal to 4000.

Abstract: A patterned epitaxial substrate includes a substrate and a plurality of patterns. The substrate has a first zone and a second zone surrounding the first zone. The first zone is disposed around a center of the substrate. The patterns and the substrate are integrally formed, and the patterns are disposed on the substrate. The patterns include a plurality of first patterns and a plurality of second patterns. The first patterns are disposed in the first zone. The second patterns are disposed in the second zone. Sizes of the first patterns are different from sizes of the second patterns.

Abstract: An ultra-reliable and low latency communications local breakout (URLLC-LBO) method and a URLLC-LBO method for a next generation radio access network (NG-RAN) are provided. The method includes: configuring a core network to establish a packet data unit (PDU) session between first user equipment (UE) and the core network; configuring the first UE to establish a URLLC service; configuring a near real-time RAN intelligent controller (near-RT RIC) to establish an F1-LBO routing process to set an LBO dedicated radio bearer (DRB) for the local URLLC service; configuring an F1-LBO virtual network function (VNF) module according to a traffic rule by the F1-LBO routing process, to establish a routing table through the F1-LBO VNF module, in which the routing table defines a relationship between a first location and a second location of the LBO DRB.

Abstract: A treatment, structure and system are provided that modify the deposition process of a material that can occur over two differing materials. In an embodiment the deposition rates may be adjusted by the treatment to change the deposition rate of one of the materials to be more in line with the deposition rate of a second one of the materials. Also, the deposition rates may be modified to be different from each other, to allow for a more selective deposition over the first one of the materials than over the second one of the materials.

Abstract: An apparatus includes a vacuum chamber, a wafer transfer mechanism, a first gas source, a second gas source and a reuse gas pipe. The vacuum chamber is divided into at least three reaction regions including a first reaction region, a second reaction region and a third reaction region. The wafer transfer mechanism is structured to transfer a wafer from the first reaction region to the third reaction region via the second reaction region. The first gas source supplies a first gas to the first reaction region via a first gas pipe, and a second gas source supplies a second gas to the second reaction region via a second gas pipe. The reuse gas pipe is connected between the first reaction region and the third reaction region for supplying an unused first gas collected in the first reaction region to the third reaction region.

Abstract: A treatment, structure and system are provided that modify the deposition process of a material that can occur over two differing materials. In an embodiment the deposition rates may be adjusted by the treatment to change the deposition rate of one of the materials to be more in line with the deposition rate of a second one of the materials. Also, the deposition rates may be modified to be different from each other, to allow for a more selective deposition over the first one of the materials than over the second one of the materials.

Abstract: An apparatus includes a vacuum chamber, a wafer transfer mechanism, a first gas source, a second gas source and a reuse gas pipe. The vacuum chamber is divided into at least three reaction regions including a first reaction region, a second reaction region and a third reaction region. The wafer transfer mechanism is structured to transfer a wafer from the first reaction region to the third reaction region via the second reaction region. The first gas source supplies a first gas to the first reaction region via a first gas pipe, and a second gas source supplies a second gas to the second reaction region via a second gas pipe. The reuse gas pipe is connected between the first reaction region and the third reaction region for supplying an unused first gas collected in the first reaction region to the third reaction region.

Abstract: A method includes forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer, depositing a dielectric layer on a bottom and along sidewalls of the trench, depositing a metal layer over the dielectric layer, depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness, applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench and removing the protection layer from the trench.

Abstract: A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is deposited in the trenches of the FinFET structure. The oxide material can be an STI oxide or a low-stress dummy gapfill material. A fin segment can be removed by an etchant and can leave a concave shaped (such as a u-shape or v-shape) portion of silicon at the bottom of the fin. Where the oxide material is an STI oxide, the void left by removing the fin can be filled with replacement STI oxide. Where the oxide material is a dummy gapfill material, the dummy gapfill material can be removed and replaced with an STI oxide or converted to an STI oxide and filled with replacement STI oxide before or after the conversion.

Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Abstract: A micro light-emitting device includes an epitaxial structure layer, a first-type electrode, a second-type electrode, and a light guide structure. The epitaxial structure layer has a top surface and a bottom surface opposite to each other and a plurality of first grooves located on the top surface. The first-type electrode and the second-type electrode separated from each other are disposed on the epitaxial structure layer and located at the bottom surface. The light guide structure is disposed on the epitaxial structure layer. The light guide structure covers a portion of the top surface and a portion of inner walls of the first grooves to define a plurality of second grooves corresponding to the portion of the first grooves.

Abstract: A patterned epitaxial substrate includes a substrate and a plurality of patterns. The substrate has a first zone and a second zone surrounding the first zone. The first zone is disposed around a center of the substrate. The patterns and the substrate are integrally formed, and the patterns are disposed on the substrate. The patterns include a plurality of first patterns and a plurality of second patterns. The first patterns are disposed in the first zone. The second patterns are disposed in the second zone. Sizes of the first patterns are different from sizes of the second patterns.

Abstract: A patterned epitaxial substrate includes a substrate and a plurality of patterns. The substrate has a first zone and a second zone surrounding the first zone. The first zone and the second zone are disposed in a concentric manner. The patterns and the substrate are integrally formed, and the patterns are disposed on the substrate. The patterns include a plurality of first patterns and a plurality of second patterns. The first patterns are disposed in the first zone. The second patterns are disposed in the second zone. Sizes of the first patterns are different from sizes of the second patterns.