Patents by Inventor Kuo-Ju Chen
Kuo-Ju Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984491Abstract: Disclosed is a method of fabricating a contact in a semiconductor device. The method includes: receiving a semiconductor structure having an opening into which the contact is to be formed; forming a metal layer in the opening; forming a bottom anti-reflective coating (BARC) layer in the opening; performing implanting operations with a dopant on the BARC layer and the metal layer, the performing implanting operations including controlling an implant energy level and controlling an implant dosage level to form a crust layer with a desired minimum depth on top of the BARC layer; removing unwanted metal layer sections using wet etching operations, wherein the crust layer and BARC layer protect remaining metal layer sections under the BARC layer from metal loss during the wet etching operations; removing the crust layer and the BARC layer; and forming the contact in the opening over the remaining metal layer sections.Type: GrantFiled: June 27, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Ju Chen, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20240154010Abstract: Embodiments of the present disclosure relates to a semiconductor device structure. The structure includes a source/drain epitaxial feature disposed over a substrate, a first interlayer dielectric (ILD) disposed over the source/drain epitaxial feature, a second ILD disposed over the first ILD. The second ILD includes a first dopant species having an atomic radius equal to or greater than silicon and a second dopant species having an atomic mass less than 15. The structure also includes a first conductive feature disposed in the second ILD, and a second conductive feature disposed over the source/drain epitaxial feature, the second conductive feature extending through the first ILD and in contact with the first conductive feature.Type: ApplicationFiled: January 22, 2023Publication date: May 9, 2024Inventors: Meng-Han Chou, Kuo-Ju Chen, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20240145596Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.Type: ApplicationFiled: January 2, 2024Publication date: May 2, 2024Inventors: Su-Hao Liu, Kuo-Ju Chen, Kai-Hsuan Lee, I-Hsieh Wong, Cheng-Yu Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang, Meng-Han Chou
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Patent number: 11973027Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.Type: GrantFiled: March 23, 2022Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Yu Chou, Jr-Hung Li, Liang-Yin Chen, Su-Hao Liu, Tze-Liang Lee, Meng-Han Chou, Kuo-Ju Chen, Huicheng Chang, Tsai-Jung Ho, Tzu-Yang Ho
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Patent number: 11955553Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.Type: GrantFiled: February 24, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
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Patent number: 11908740Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes source/drain structures on opposite sides of the gate structure. The semiconductor structure also includes a dielectric layer over the gate structure and the source/drain structures. The semiconductor structure also includes a via plug passing through the dielectric layer and including a first group IV element. The dielectric layer includes a second group IV element, a first compound, and a second compound, and the second compound includes elements in the first compound and the first group IV element.Type: GrantFiled: November 25, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Po Hsieh, Su-Hao Liu, Hong-Chih Liu, Jing-Huei Huang, Jie-Huang Huang, Lun-Kuang Tan, Huicheng Chang, Liang-Yin Chen, Kuo-Ju Chen
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Publication number: 20240055300Abstract: A method includes forming a fin structure over a substrate; depositing a dummy gate layer over the substrate and the fin structure; depositing a hard mask stack over the dummy gate layer; depositing a photoresist bottom layer over the hard mask stack, wherein the photoresist bottom layer has a first stress; performing an implantation process to the photoresist bottom layer to form an implanted bottom layer with a second stress closer to 0 than the first stress; patterning the implanted bottom layer; patterning the hard mask stack and the dummy gate layer by using the patterned implanted bottom layer as an etch mask to form a dummy gate structure over the fin structure; and replacing the dummy gate structure with a metal gate structure.Type: ApplicationFiled: August 12, 2022Publication date: February 15, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Ting CHANG, Kuo-Ju CHEN, Tien-Shun CHANG, Su-Hao LIU, Huicheng CHANG
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Patent number: 11901455Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.Type: GrantFiled: July 20, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Su-Hao Liu, Kuo-Ju Chen, Kai-Hsuan Lee, I-Hsieh Wong, Cheng-Yu Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang, Meng-Han Chou
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Publication number: 20240030312Abstract: A method includes forming a fin structure over a substrate; depositing a dummy gate layer over the substrate and the fin structure; etching back the dummy gate layer; performing an implantation process to the dummy gate layer to form an implantation region in the dummy gate layer, wherein a vertical thickness of the dummy gate layer is greater than a vertical thickness of the implantation region; forming a patterned hard mask stack over the implantation region; patterning the implantation region and the dummy gate layer by using the patterned hard mask stack as an etch mask to form a dummy gate structure over the fin structure; and replacing the dummy gate structure with a metal gate structure.Type: ApplicationFiled: July 22, 2022Publication date: January 25, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Ju CHEN, Wei-Ting CHANG, Po-Kang HO, Su-Hao LIU, Yee-Chia YEO
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Patent number: 11862694Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.Type: GrantFiled: April 6, 2021Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20230420540Abstract: Disclosed is a method of fabricating a contact in a semiconductor device. The method includes: receiving a semiconductor structure having an opening into which the contact is to be formed; forming a metal layer in the opening; forming a bottom anti-reflective coating (BARC) layer in the opening; performing implanting operations with a dopant on the BARC layer and the metal layer, the performing implanting operations including controlling an implant energy level and controlling an implant dosage level to form a crust layer with a desired minimum depth on top of the BARC layer; removing unwanted metal layer sections using wet etching operations, wherein the crust layer and BARC layer protect remaining metal layer sections under the BARC layer from metal loss during the wet etching operations; removing the crust layer and the BARC layer; and forming the contact in the opening over the remaining metal layer sections.Type: ApplicationFiled: June 27, 2022Publication date: December 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Ju Chen, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
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Patent number: 11854870Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.Type: GrantFiled: August 30, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Cheng Chou, Yu-Fang Huang, Kuo-Ju Chen, Ying-Liang Chuang, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20230411474Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.Type: ApplicationFiled: August 7, 2023Publication date: December 21, 2023Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20230386898Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Cheng Chou, Yu-Fang Huang, Kuo-Ju Chen, Ying-Liang Chuang, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20230387251Abstract: A method for manufacturing a semiconductor device includes: forming a patterned structure on a substrate, the patterned structure including a dielectric layer and a dummy gate structure disposed in the dielectric layer; and subjecting the patterned structure to an ion implantation process so as to modulate a profile of the dummy gate structure.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tien-Shun CHANG, Kuo-Ju CHEN, Sih-Jie LIU, Wei-Fu WANG, Yi-Chao WANG, Li-Ting WANG, Su-Hao LIU, Huicheng CHANG, Yee-Chia YEO
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Publication number: 20230369103Abstract: A connecting structure includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Kuo-Ju Chen, Chun-Hsien Huang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20230352533Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.Type: ApplicationFiled: July 12, 2023Publication date: November 2, 2023Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Miao Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
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Patent number: 11791204Abstract: A connecting structure includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants.Type: GrantFiled: February 9, 2021Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Ju Chen, Chun-Hsien Huang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20230327021Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.Type: ApplicationFiled: June 16, 2023Publication date: October 12, 2023Inventors: Chao-Hsun Wang, Chen-Ming Lee, Kuo-Yi Chao, Mei-Yun Wang, Pei-Yu Chou, Kuo-Ju Chen
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Publication number: 20230317519Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee