Abstract: Some implementations described herein provide techniques and apparatuses for polishing a perimeter region of a semiconductor substrate so that a roll-off profile at or near the perimeter region of the semiconductor substrate satisfies a threshold. The described implementations include depositing a first layer of a first oxide material across the semiconductor substrate followed by depositing a second layer of a second oxide material over the first layer of the first oxide material and around a perimeter region of the semiconductor substrate. The described implementations further include polishing the second layer of the second oxide material over the perimeter region using a chemical mechanical planarization tool including one or more ring-shaped polishing pads oriented vertically over the perimeter region.

Abstract: A semiconductor device is provided. The semiconductor device comprises an output circuit configured to be electrically connected between a driving circuit and an external load circuit, and a protection circuit electrically connected to the output circuit and the driving circuit. The protection circuit comprises a first transistor having a base electrode, a collector electrode and an emitter electrode and a second transistor having a base electrode, a collector electrode and an emitter electrode. The base electrode of the first transistor is electrically connected to the collector electrode of the second transistor.

Abstract: A device and methods of forming the same are described. The device includes a substrate and a first bipolar junction transistor (BJT) disposed over the substrate. The first BJT includes a first base region, a first emitter region, and a first collector region. The device further includes a second BJT disposed over the substrate adjacent the first BJT, and the second BJT includes a second base region, a second emitter region, and a second collector region. The device further includes an interconnect structure disposed over the first and second BJTs, and the interconnect structure includes a first conductive line electrically connected to the first emitter region and the second base region and a second conductive line electrically connected to the first collector region and the second collector region.

Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

Abstract: In a color display, a color filter layer includes a dielectric layer with an array of photonic crystals, an electroluminescent material disposed on the color filter layer, and electrodes arranged to electrically energize the electroluminescent material to output white light. Each photonic crystal includes a two-dimensional (2D) array of features. The 2D array of features includes a central cavity within which the features of the 2D array of features are omitted. Each photonic crystal is tuned to a resonant wavelength by a periodicity of the two-dimensional array of features. The array of photonic crystals may include, for example, red, green, and blue photonic crystals arranged to form an array of pixels spanning a display area of the color display, in which each pixel includes at least one red photonic crystal, at least one green photonic crystal, and at least one blue photonic crystal.

Abstract: In a color display, a color filter layer includes a dielectric layer with an array of photonic crystals, an electroluminescent material disposed on the color filter layer, and electrodes arranged to electrically energize the electroluminescent material to output white light. Each photonic crystal includes a two-dimensional (2D) array of features. The 2D array of features includes a central cavity within which the features of the 2D array of features are omitted. Each photonic crystal is tuned to a resonant wavelength by a periodicity of the two-dimensional array of features. The array of photonic crystals may include, for example, red, green, and blue photonic crystals arranged to form an array of pixels spanning a display area of the color display, in which each pixel includes at least one red photonic crystal, at least one green photonic crystal, and at least one blue photonic crystal.

Abstract: In some embodiments, the present disclosure relates to a method that includes bonding a first wafer to a second wafer to form a wafer stack and removing a top portion of the second wafer. A first trim blade having a first blade width is aligned over the second wafer. The first trim blade is used to form a trench that separates a central portion of the second wafer from a peripheral portion of the second wafer. The trench is arranged at a first distance from an outer perimeter of the second wafer, and extends from a top surface of the second wafer to a trench depth beneath the top surface of the first wafer. A second trim blade having a second blade width is aligned over the peripheral portion, the second blade width being greater than the first blade width. The peripheral portion is removed using the second trim blade.

Abstract: In a color display, a color filter layer includes a dielectric layer with an array of photonic crystals, an electroluminescent material disposed on the color filter layer, and electrodes arranged to electrically energize the electroluminescent material to output white light. Each photonic crystal includes a two-dimensional (2D) array of features. The 2D array of features includes a central cavity within which the features of the 2D array of features are omitted. Each photonic crystal is tuned to a resonant wavelength by a periodicity of the two-dimensional array of features. The array of photonic crystals may include, for example, red, green, and blue photonic crystals arranged to form an array of pixels spanning a display area of the color display, in which each pixel includes at least one red photonic crystal, at least one green photonic crystal, and at least one blue photonic crystal.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes bonding a first semiconductor wafer to a second semiconductor wafer. A bond interface is disposed between the first and second semiconductor wafers. The first semiconductor wafer has a peripheral region laterally surrounding a central region. A support structure is formed between a first outer edge of the first semiconductor wafer and a second outer edge of the second semiconductor wafer. The support structure is disposed within the peripheral region. A thinning process is performed on the second semiconductor wafer.

Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region adjacent to the drain region; a gate electrode over the substrate and further downwardly extends into the substrate, wherein a portion of the gate electrode below a top surface of the substrate abuts the isolation region; and a source region and a drain region formed in the substrate on either side of the gate structure. An associated method for fabricating the semiconductor structure is also disclosed.

Abstract: Certain aspects of the present invention are directed to improved processes for preparing enantiomerically enriched intermediates for the synthesis of ruxolitinib and deuterated forms of ruxolitinib. Certain aspects are also directed to deuterated intermediates useful in the synthesis of deuterated forms of ruxolitinib. Certain aspects are also directed to reaction mixtures for preparing enantiomerically enriched intermediates useful in the synthesis of ruxolitinib and deuterated forms of ruxolitinib.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A dielectric protection layer is along a sidewall of the interconnect structure and along a sidewall and a recessed surface of the substrate. A bottommost surface of the dielectric protection layer rests on the recessed surface of the substrate.

Abstract: In an embodiment, a device includes: a gallium nitride device on a substrate, the gallium nitride device including an electrode; a dielectric layer on and around the gallium nitride device; an isolation layer on the dielectric layer; a semiconductor layer on the isolation layer, the semiconductor layer including a silicon device; a through via extending through the semiconductor layer, the isolation layer, and the dielectric layer, the through via electrically and physically coupled to the electrode of the gallium nitride device; and an interconnect structure on the semiconductor layer, the interconnect structure including metallization patterns electrically coupled to the through via and the silicon device.

Abstract: A gate-all-around (GAA) high voltage transistor of the laterally double-diffused metal-oxide semiconductor (LDMOS) type has a loop-shaped gate electrode disposed below a surface of a semiconductor substrate. The loop-shaped gate electrode surrounds a vertical channel formed by a first source/drain region, a body region, and a diffusion region. The first source/drain region is on top, the body region is in the middle, and the diffusion region is underneath. A loop-shaped shallow trench isolation (STI) region surrounds the loop-shaped gate electrode. The diffusion region begins inside the loop-shaped gate electrode, extends under the loop-shaped gate electrode and the loop-shaped STI region, and rises outside the loop-shaped STI region to join with a second source/drain region. This structure allows pitch to be reduced by 40% or linear drive current to be doubled in comparison to an asymmetric NMOS transistor providing otherwise equivalent functionality.

Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region adjacent to the drain region; a gate electrode over the substrate and further downwardly extends into the substrate, wherein a portion of the gate electrode below a top surface of the substrate abuts the isolation region; and a source region and a drain region formed in the substrate on either side of the gate structure. An associated method for fabricating the semiconductor structure is also disclosed.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having an upper surface and a recessed surface extending in a closed loop around the upper surface. The recessed surface is vertically between the upper surface and a lower surface of the first substrate opposing the upper surface. A first plurality of interconnects are disposed within a first dielectric structure on the upper surface. A dielectric protection layer is over the recessed surface, along a sidewall of the first dielectric structure, and along a sidewall of the first substrate. The first substrate extends from directly below the dielectric protection layer to laterally outside of the dielectric protection layer.

Abstract: The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.

Abstract: A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.