Abstract: A combinatorial processing chamber is provided. The combinatorial processing chamber is configured to isolate a radial portion of a rotatable substrate support, which in turn is configured to support a substrate. The chamber includes a plurality of clusters process heads in one embodiment. An insert having a base plate disposed between the substrate support and the process heads defines a confinement region for a deposition process in one embodiment. The base plate has an opening to enable access of the deposition material to the substrate. Through rotation of the substrate and movement of the opening, multiple regions of the substrate are accessible for performing combinatorial processing on a single substrate.

Abstract: A structure for independently supporting a wafer and a mask in a processing chamber is provided. The structure includes a set of extensions for supporting the wafer and a set of extensions supporting the mask. The set of extensions for the wafer and the set of extensions for the mask enable independent movement of the wafer and the mask. In one embodiment, the extensions are affixed to an annular ring which is capable of moving in a vertical direction within the processing chamber. A processing chamber, a mask, and a method for combinatorially processing a substrate are also provided.

Abstract: A method for analyzing and optimizing fabrication techniques using variations of materials, unit processes, and process sequences is provided. In the method, a subset of a semiconductor manufacturing process sequence and build is analyzed for optimization. During the execution of the subset of the manufacturing process sequence, the materials, unit processes, and process sequence for creating a certain structure is varied. During the combinatorial processing, the materials, unit processes, or process sequence is varied between the discrete regions of a semiconductor substrate, wherein within each of the regions the process yields a substantially uniform or consistent result that is representative of a result of a commercial manufacturing operation. A tool for optimizing a process sequence is also provided.

Abstract: A method for analyzing and optimizing fabrication techniques using variations of materials, unit processes, and process sequences is provided. In the method, a subset of a semiconductor manufacturing process sequence and build is analyzed for optimization. During the execution of the subset of the manufacturing process sequence, the materials, unit processes, and process sequence for creating a certain structure is varied. During the combinatorial processing, the materials, unit processes, or process sequence is varied between the discrete regions of a semiconductor substrate, wherein within each of the regions the process yields a substantially uniform or consistent result that is representative of a result of a commercial manufacturing operation. A tool for optimizing a process sequence is also provided.

Abstract: One embodiment relates to a scanning electron beam apparatus having curved electron-optical axes. An electron gun and illumination electron optics are configured to generate a primary electron beam along a first axis. Objective electron optics is configured about a second axis to receive the primary electron beam, to focus the incident electron beam onto the substrate, and to retrieve an emitted beam of scattered electrons from the substrate. Detection electron optics is configured about a third axis to receive the emitted beam and to focus the emitted beam onto a detector. A beam separator is coupled to and interconnecting the illumination electron optics, the objective electron optics, and the detection electron optics in such a way that there is a same angle between the first and second axes as between the second and third axes. A beam deflector is configured to controllably scan the primary electron beam across the substrate and to de-scan the emitted electron beam. Other embodiments are also disclosed.

Abstract: The invented method produces a silicide region on a silicon body that is useful for a variety of purposes, including the reduction of the electrical contact resistance to the silicon body or an integrated electronic device formed thereon. The invented method includes a step of producing an amorphous region on the silicon body using ion implantation, for example, a step of forming a metal layer such as titanium, cobalt or nickel in contact with the amorphous region, and a step of irradiating the metal with intense light from a source such as a laser, to cause metal atoms to diffuse into the amorphous region to form an alloy region with a silicide composition. In an application of the invented method to the manufacture of a MISFET device, the metal layer is preferably formed with a thickness that is at least sufficient to produce a stoichiometric proportion of metal and silicon atoms in the amorphous region of the gate of the MISFET device.

Abstract: The invented method can be used to form silicide contacts to an integrated MISFET device. Field isolation layers are formed to electrically isolate a portion of the silicon substrate, and gate, source and drain regions are formed therein. A polysilicon runner(s) that makes an electrical connection to the integrated device, is formed on the isolation layers. The structure is subjected to ion implantation to amorphized portions of the silicon gate, source, drain and runner regions. A metal layer is formed in contact with the amorphized regions, and the metal layer overlying the active region of the integrated device is selectively irradiated using a mask. The light melts part of the gate, and amorphized source and drain regions while the remaining portions of the integrated device and substrate remain in their solid phases. Metal diffuses into the melted gate, source and drain regions which are thus converted into respective silicide alloy regions.

Abstract: The invented method produces a silicide region on a silicon body that is useful for a variety of purposes, including the reduction of the electrical contact resistance to the silicon body or an integrated electronic device formed thereon. The invented method includes a step of producing an amorphous region on the silicon body using ion implantation, for example, a step of forming a metal layer such as titanium, cobalt or nickel in contact with the amorphous region, and a step of irradiating the metal with intense light from a source such as a laser, to cause metal atoms to diffuse into the amorphous region to form an alloy region with a silicide composition. In an application of the invented method to the manufacture of a MISFET device, the metal layer is preferably formed with a thickness that is at least sufficient to produce a stoichiometric proportion of metal and silicon atoms in the amorphous region of the gate of the MISFET device.

Abstract: A method for fabricating a plurality of shallow-junction metal oxide semiconductor field-effect transistors (MOSFETs) on a selected area of a silicon wafer, in the case in which the MOSFETs are spaced from one another by substantially transparent isolation elements. The method includes the step of flooding the entire selected area with laser radiation that is intended to effect the heating to a desired threshold temperature of only the selected depth of a surface layer of silicon that has been previously amorphized to this selected depth and then doped. This threshold temperature is sufficient to melt amorphized silicon but is insufficient to melt crystalline silicon.

Abstract: Pre-amorphization of a surface layer of crystalline silicon to an ultra-shallow (e.g., less than 100 nm) depth provides a solution to fabrication problems including (1) high thermal conduction in crystalline silicon and (2) shadowing and diffraction-interference effects by an already fabricated gate of a field-effect transistor on incident laser radiation. Such problems, in the past, have prevented prior-art projection gas immersion laser doping from being effectively employed in the fabrication of integrated circuits comprising MOS field-effect transistors employing 100 nm and shallower junction technology.

Abstract: The method of this invention produces a silicide region on a silicon body that is useful for a variety of purposes, including the reduction of the electrical contact resistance to the silicon body or an integrated electronic device formed thereon. The invented method includes the steps of producing an amorphous region on the silicon body using ion implantation, for example, forming or positioning a metal such as titanium, cobalt or nickel in contact with the amorphous region, and irradiating the metal with intense light from a laser source, for example, to cause metal atoms to diffuse into the amorphous region. The amorphous region thus becomes an alloy region with the desired silicide composition. Upon cooling after irradiation, the alloy region becomes partially crystalline. To convert the alloy region into a more crystalline form, the invented method preferably includes a step of treating the alloy region using rapid thermal annealing, for example.