Abstract: A coil component includes a body, a support substrate embedded in the body and having one end surface exposed to an external surface of the body, a coil portion disposed on the support substrate to be embedded in the body and having one end portion exposed to the external surface of the body together with the one end surface of the support substrate, and an external electrode disposed on the external surface of the body to be connected to the one end portion of the coil portion. The external electrode has an opening exposing at least a portion of the one end surface of the support substrate.

Abstract: Disclosed is a lane departure warning determination method using driver state monitoring, which includes (a) recognizing a lane around a vehicle from an image photographed by a lane recognition camera and extracting lane information; (b) extracting facial feature points of a driver from an image photographed by a driver recognition camera; (c) determining from the lane information whether the vehicle is in a lane departure state or a lane approaching state; (d) when it is determined in step (c) that the vehicle is in the lane departure state, generating a warning when a face tilt of the driver exceeds a first angle; and (e) when it is determined in step (c) that the vehicle is in the lane approaching state, generating a warning when the face tilt of the driver exceeds a second angle.

Abstract: A coil component includes a body having both end surfaces opposing each other in a length direction; a support substrate disposed in the body; a coil portion disposed on the support substrate in a width direction of the body, and including first and second lead-out portions each exposed to a first surface and a second surface of the body opposing each other in a thickness direction of the body, respectively, and disposed on the support substrate; and first and second external electrodes disposed on the first surface of the body, spaced apart from each other, and connected to one ends of the first and second lead-out portions exposed to the first surface of the body, respectively.

Abstract: In one example embodiment, a semiconductor system includes a first chip configured to generate first temperature information of the first chip, the first temperature information being based on at least one temperature measurement using at least one first temperature sensor. The semiconductor system further includes a second chip including a second temperature sensor configured to be controlled based on at least the first temperature information.

Abstract: A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

Abstract: A coil electronic component includes a coil including upper and lower coils and a via electrically connecting the upper and lower coils to each other. The via is formed along at least a portion of a boundary surface of a through-hole penetrating upper and lower surfaces of a support member supporting the upper and lower coils.

Abstract: Disclosed is a lane departure warning determination method using driver state monitoring, which includes (a) recognizing a lane around a vehicle from an image photographed by a lane recognition camera and extracting lane information; (b) extracting facial feature points of a driver from an image photographed by a driver recognition camera; (c) determining from the lane information whether the vehicle is in a lane departure state or a lane approaching state; (d) when it is determined in step (c) that the vehicle is in the lane departure state, generating a warning when a face tilt of the driver exceeds a first angle; and (e) when it is determined in step (c) that the vehicle is in the lane approaching state, generating a warning when the face tilt of the driver exceeds a second angle.

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

Abstract: A coil component includes a body having a first surface and a second surface facing each other, and having a plurality of wall surfaces connecting the first surface to the second surface; an insulating substrate; a coil portion comprising a first lead-out pattern and a second lead-out pattern each covered with the body and disposed on the insulating substrate; a first external electrode and a second external electrode disposed on the first surface of the body and spaced apart from each other; a first connection electrode and a second connection electrode respectively extending from the first and second lead-out patterns to the first and second external electrodes; and a first support portion and a second support portion respectively extending from the coil portion to be exposed to one of the plurality of wall surfaces, and respectively disposed to be spaced apart from the first and second lead-out patterns.

Abstract: A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.

Abstract: A coil electronic component includes a support substrate having a through-hole. First and second coil patterns are disposed on a first surface and a second surface of the support substrate opposing each other, respectively, and each surround the through-hole and are coiled. An encapsulant encapsulates at least portions of the support substrate and the first and second coil patterns, and external electrodes are disposed externally of the encapsulant and are each connected to a respective lead-out pattern connected to a respective one of the first and second coil patterns. A groove penetrates the first surface of the support substrate in a region of the first surface in which the first coil pattern is not disposed, and the second coil pattern is disposed in a region of the second surface of the support substrate that overlaps along a thickness direction with the groove penetrating the first surface.

Abstract: A coil electronic component includes a support substrate having a first surface and a second surface opposing each other, a coil pattern disposed on the first surface of the support substrate, first and second conductive vias penetrating the support substrate and connected to one end and the other end of the coil pattern, respectively, an encapsulant encapsulating the support substrate and the coil pattern, and first and second external electrodes disposed on a lower surface of the encapsulant and electrically connected to the first and second conductive vias, respectively. The support substrate is disposed between the lower surface of the encapsulant and the coil pattern.

Abstract: A coil component includes a body having one surface and another surface opposing each other in one direction, a plurality of walls each connecting the one surface to the other surface, and a coil portion disposed therein. A recess extends along at least portions of edges common to the one surface and to walls of the plurality of walls. A lower insulating layer is disposed in the recess and on the one surface. First and second external electrodes penetrate through the lower insulating layer, are spaced apart from each other on the one surface of the body, and are connected to the coil portion. A shielding layer is disposed on the other surface of the body and the plurality of walls of the body, and extends to the one surface of the body to be spaced apart from the first and second external electrodes.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.

Abstract: The present invention relates to a pedestrian recognition apparatus. A pedestrian recognition apparatus may comprises: an image receiving unit configured to sequentially receive a plurality of images from a camera; and a pedestrian determination unit configured to perform a pedestrian candidate object detection process of detecting a pedestrian candidate object from one or more objects in the images, a mobility determination process of determining whether the pedestrian candidate object is moving, using the plurality of images, and setting the pedestrian candidate object to a moving pedestrian candidate object, and a pedestrian possibility determination process of performing a predefined operation on the moving pedestrian candidate object, and setting the moving pedestrian candidate object to a pedestrian when a value calculated through the predefined operation is equal to or more than a threshold value.

Abstract: The present invention relates to a pharmaceutical composition comprising a maple leaf extract or fraction thereof for preventing or treating a retinal disease, a method for preventing or treating a retinal disease using the pharmaceutical composition, and a food composition comprising a maple leaf extract or fraction thereof for ameliorating the symptoms of a retinal disease. The pharmaceutical composition according to the present invention, which is effective for the treatment of a retinal disease, can be used pharmaceutically as a composition for preventing or treating a retinal disease, and can also be used advantageously as a health functional food.

Abstract: Memory devices and methods of operating the same are provided. The memory device including at least one internal circuit including a memory cell array and a peripheral circuit configured to drive the memory cell array, a monitor logic configured to monitor a current flowing into the at least one internal circuit and output a monitoring result, a detect logic configured to detect whether a leakage current flows in the at least one internal circuit based on the monitoring result, and output detected information regarding the leakage current, and diagnosis logic configured to diagnose an error in the at least one internal circuit based on the detected information.

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

Abstract: A coil electronic component includes a body and external electrodes disposed on an external surface of the body. The body includes a support member including a through-hole, upper and lower coils supported by the support member and including a plurality of coil patterns, a via connecting the upper and lower coils to each other, and an insulating wall supported by the support member and insulating adjacent coil patterns from each other. The via is formed on at least a portion of a interface of the through-hole.