Abstract: A memory device, system, and/or method are provided for performing a page state informing function. The memory device may compare one or more row addresses received along with a command, determine the page open/close state according to a page hit or miss generated as a result of comparison, count read or write commands with respect to pages corresponding to a same row address, and determine the page open/close state according to a read or write command number generated as a result of counting. The memory device may determine a page open/close state with respect to a corresponding page based on a page hit/miss and a read or write command number and output a flag signal. The memory device may provide the page open/close state for each channel. A memory controller may establish different page open/close policies for each channel.

Abstract: A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

Abstract: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

Abstract: The present invention can improve the recognition performance of a traffic sign board, improve the recognition performance of a reflective traffic sign board and a light emitting type traffic sign board by adjusting an exposure of a camera, improve the recognition performance of the reflective traffic sign board and the light emitting type traffic sign board by adjusting gain of an image signal, and improve the recognition performance of the reflective traffic sign board and the light emitting type traffic sign board by simultaneously adjusting the exposure of the camera and the gain of the image signal.

Abstract: A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.

Abstract: Disclosed is a mobile communication terminal having a light guide plate for indicating the receipt of a signal. This mobile communication terminal comprises an upper frame. A light guide plate is mounted in the upper frame. The light guide plate has an opening corresponding to a region of an image display window. In addition, at least one LED is arranged adjacent to the light guide plate so as to introduce light into the light guide plate. Since the light guide plate is used for indicating the receipt of a signal, it is possible to provide a mobile communication terminal allowing a user to easily recognize a state where a signal has been received.

Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

Abstract: A navigation system may include: a GPS module; an image recognition module having a line recognition function; a roadmap storage module configured to store roadmap information and route change possible section information through which a route of a vehicle is changed; a roadmap receiving module configured to receive the roadmap information; and an arithmetic processing module configured to determine whether the route of the vehicle is changed, based on the route change possible section information and line recognition information recognized by the image recognition module.

Abstract: Provided is a GPS correction system and method which corrects position information obtained from a low-precision GPS device using image recognition information. The GPS correction system using image recognition system includes: a GPS module; an image recognition device having a line recognition function; a road map storage unit configured to store road map information including line characteristic information or a road map receiving unit configured to receive the road map information; and an information processing device configured to compare the line recognition information acquired through the image recognition device to the line characteristic information, correct a current position measured by the GPS module, and calculate traveling lane information.

Abstract: An aspherical lens includes a light entrance plane configured to receive light emitted from a light source and a light exit plane configured to radiate the light received by the light entrance plane. The light exit plane includes semispherical convex portions disposed on an upper surface of the aspherical lens, a concavely depressed portion comprising an overlapping region where the semispherical convex portions partially overlap each other at a central axis, a side portion connected with the semispherical convex portions, and an upper surface of each of the semispherical convex portions having a first flat portion.

Abstract: Provided is a route change determination system and method using image recognition information, which is capable of extracting position information having high precision similar to that of a high-precision DGPS device, while using a low-precision GPS device, in order to determine a change of a traveling route. The route change determination system using image recognition system includes: a GPS module; an image recognition module having a line recognition function; a road map storage module configured to store road map information and route change possible section information for changing a route of a vehicle; a road map receiving module configured to receive the road map information; and an information processing module configured to determine whether the route is changed or not, based on line recognition information acquired through the image recognition module and the route change possible section information.

Abstract: An integrated circuit device includes an external power supply input configured to be coupled to an external power supply and a digital circuit, such as a clock signal generator circuit, that generates noise at a power supply input thereof. The device further includes a replica load circuit and a power supply circuit coupled to the external power supply input, to a power supply input of the digital circuit and to a power supply input of the replica load circuit. The power supply circuit is configured to selectively couple the external power supply node to the power supply input of the digital circuit responsive to a voltage at the power supply input of the replica load circuit. The replica load circuit may be configured to provide a load that varies responsive to a voltage at the power supply input of the digital circuit.

Abstract: A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

Abstract: Exemplary embodiments of the present invention relate to an aspherical light emitting diode (LED) lens and a light emitting device including the same. The aspherical LED lens includes a light exit plane concavely depressed near a central axis, a light entrance plane including a conical plane having a vertex located on the central axis, and a plurality of protrusions arranged on a portion of a side surface of the light exit plane. The aspherical LED lens has a radially symmetrical structure with respect to the central axis.

Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.

Abstract: Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time.

Abstract: There is provided a light emitting diode package having at least two heat sinks. The light emitting diode package includes a main body, at least two lead terminals fixed to the main body, and at least two heat sinks of electrically and thermally conductive materials, the heat sinks being fixed to the main body. The at least two heat sinks are separated from each other. Thus, high luminous power can be obtained mounting a plurality of light emitting diode dies in one LED package. Further, it is possible to embody polychromatic lights mounting LED dies emitting different wavelengths of light each other in the LED package.

Abstract: At least one example embodiment discloses a stacked memory device including a plurality of stacked memory chips, each of the memory chips including a memory array, a plurality of through silicon vias (TSVs) operatively connected to the plurality of stacked memory chips, micro channels configured to access the memory arrays and at least one circuit in each memory chip, the at least one circuit configured to vary a number of the micro channels accessing the memory array.

Abstract: A memory device includes an input/output (I/O) interface, a secure logic for receiving a storage verifying command including an expected value of secure data via the I/O interface, an I/O logic for receiving an input request for inputting user data into the memory device and/or an output request for outputting user data therefrom and perform one of the input request and/or the output request, and a memory unit including a secure area, accessible by the secure logic, for storing the secure data and a normal area, accessible by the I/O logic, for storing the user data. The secure logic reads the secure data from the secure area in response to the input of the storage verifying command and outputs a storage verifying result to the external device, without outputting the secure data to the external device, according to whether the secure data expected value is identical with the secure data.

Abstract: A data mask system includes a processor providing control signals including a command signal, an address signal, and a data signal, a data mask processor receiving the control signals and providing either write data or masked data in response to the control signals, and generating data mask information and a data mask selection signal from at least one of the control signals, and a data mask register unit receiving the data mask selection signal, storing the data mask information, selecting a subset of the stored data mask information in response to the data mask selection signal, and returning selected data mask information to the data mask processor. The data mask processor receives the selected data mask information from the data mask register unit and provides the masked data as a result of performing a data mask operation on the data signal according to the selected data mask information.