Abstract: A semiconductor device includes a sampling code generation circuit and a code comparator. The sampling code generation circuit includes a buffer circuit configured to receive an external set signal. The sampling code generation circuit is configured to perform a count operation during a sampling period, the sampling period adjusted based on an output signal of the buffer circuit to generate a sampling code. The code comparator is configured to compare the sampling code with a reference code to generate a comparison flag.

Abstract: An electronic system includes a reception device and a transmission device. The reception device generates reception data from transmission data input to a reception node and includes a termination circuit which is coupled to the reception node to perform an impedance matching operation. The transmission device generates a drive control signal from internal data based on a mode signal and drives the transmission data based on the drive control signal.

Abstract: An electronic system includes a reception device and a transmission device. The reception device generates reception data from transmission data input to a reception node and includes a termination circuit which is coupled to the reception node to perform an impedance matching operation. The transmission device generates a drive control signal from internal data based on a mode signal and drives the transmission data based on the drive control signal.

Abstract: A communications device and a data receiving method thereof are provided. The communications device includes: a receiver antenna receiving data; a receiver phase shifter forming a first sum beam and a first difference beam based on a first estimated direction-of-arrival (DOA); a receiver radio frequency (RF) chain generating first difference beam output using the first difference beam formed during a first data period of the received data and generating first sum beam output using the first sum beam formed in a second data period of the received data, which is different from the first data period; and a receiver controller calculating an offset vector between an actual DOA and the first estimated DOA based on the first difference beam output and the first sum beam output.

Abstract: A duty cycle correction circuit may include a data alignment circuit, a correction value generation circuit, and a dock generation circuit. The data alignment circuit may align unit pattern data based on a strobe clock signal. The correction value generation circuit may generate a duty correction value by measuring the amount of charges corresponding to the aligned data. The clock generation circuit may correct the duty ratio of the strobe clock signal based on the duty correction value.

Abstract: A memory device includes a clock generating circuit suitable for generating a plurality of internal clock signals based on an external clock signal during an output period of read data, in response to a read command, and a data strobe output circuit suitable for outputting a first data strobe signal to a data strobe pad in response to the internal clock signals, wherein the internal clock signals toggle regardless of the output period of the read data, in response to a test mode signal.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a chip selection signal, a command/address signal and a clock signal. The first semiconductor device outputs first external data and a strobe signal during a write operation in a test mode and receives second external data to adjust an output moment of the strobe signal during a read operation in the test mode. The second semiconductor device is synchronized with the strobe signal to latch input data generated from the first external data during the write operation according to the chip selection signal and the command/address signal. The second semiconductor device generates output data from the input data and outputs the output data as the second external data during the read operation according to the chip selection signal and the command/address signal.

Abstract: A memory device may include a clock dividing circuit suitable for generating a plurality of internal clocks by dividing an external clock, a mode decision circuit suitable for determining an operation mode according to an input time point of a read command based on the internal clocks, a clock arranging circuit suitable for arranging the internal clocks in an order determined according to the operation mode, and outputting the arranged clocks as a plurality of data output clocks, and a data arranging circuit suitable for arranging read data according to the operation mode, and outputting the arranged data in response to the data output clocks.

Abstract: A communications device and a data receiving method thereof are provided. The communications device includes: a receiver antenna receiving data; a receiver phase shifter forming a first sum beam and a first difference beam based on a first estimated direction-of-arrival (DOA); a receiver radio frequency (RF) chain generating first difference beam output using the first difference beam formed during a first data period of the received data and generating first sum beam output using the first sum beam formed in a second data period of the received data, which is different from the first data period; and a receiver controller calculating an offset vector between an actual DOA and the first estimated DOA based on the first difference beam output and the first sum beam output.

Abstract: A clock generation circuit includes: a preliminary clock generation circuit suitable for generating a first preliminary clock signal with a half of a target cycle, and generating a second preliminary clock signal by inverting the first preliminary clock signal; a clock doubler circuit suitable for generating first and second intermediate clock signals by respectively doubling the cycles of the first and second preliminary clock signals; and an edge trigger circuit suitable for triggering the first and second intermediate clock signals to output first and second output clock signals with the target cycle, respectively, according to the first and second preliminary clock signals.

Abstract: A semiconductor memory device includes: an internal circuit; a write control circuit suitable for writing write data into the internal circuit based on a write strobe signal during a normal write operation, and writing test data into the internal circuit based on a read strobe signal during a test write operation; and a read control circuit suitable for generating the read strobe signal and outputting the read strobe signal together with read data read from the internal circuit during a normal read operation or a test read operation, and generating the read strobe signal and providing the write control circuit with the read strobe signal during the test write operation.

Abstract: A scheduling method for grant-free multiple access, and a user terminal for the same are disclosed. The method comprises: (a) a step of receiving, from the user terminal, information on traffic to be served, network information of the user terminal and state information of the user terminal; (b) a scheduling step of forming scheduling groups on the basis of the information received in step (a) and a step of allocating resources to each scheduling group; and (c) providing scheduling information to the user terminal, wherein traffic aggregations for traffic of the terminal are set on the basis of the information on traffic from the terminal, the scheduling groups are formed according to the traffic aggregations, and the scheduling information is provided to each traffic aggregation by which the user terminal is to be served.

Abstract: A memory device includes a clock generating circuit suitable for generating a plurality of internal clock signals based on an external clock signal during an output period of read data, in response to a read command, and a data strobe output circuit suitable for outputting a first data strobe signal to a data strobe pad in response to the internal clock signals, wherein the internal clock signals toggle regardless of the output period of the read data, in response to a test mode signal.

Abstract: A memory device includes a plurality of memory cell arrays, a plurality of data transmitters corresponding to the plurality of memory cell arrays, respectively, and suitable for transmitting data read in parallel from the corresponding memory cell arrays, and a test circuit suitable for selecting one data transmitter among the plurality of data transmitters, and sequentially outputting data transmitted in parallel from the selected data transmitter to one data input/output pad among a plurality of data input/output pads, during a test mode.

Abstract: A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal. The second buffer may generate a second data strobe buffering signal based on the first input signal and a reference xvoltage. The divider circuit may divide the second data strobe buffering signal to generate a divided signal and a divided bar signal. The internal signal generation circuit may be configured to generate a first to fourth data latch timing signals having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided buffering signal.

Abstract: The present invention relates to a method by which a movable object that is within a wireless network and capable of communicating with other movable objects uses the relative distance and azimuth angle information of the movable objects to estimate its self-location, as well as to the movable object capable of estimating its self-location. A self-location estimation method according to an embodiment of the present invention can be a method used by a movable object within a wireless network environment that enables communication between movable objects and can include: receiving the location information of a counterpart movable object from the counterpart movable object; measuring the relative distance and relative azimuth angle of the counterpart movable object; and deriving the current location information of the movable object by using the received location information of the counterpart movable object and the measured relative distance and relative azimuth angle.

Abstract: Disclosed are method and apparatus for enabling multiple access in a wireless communication system that can enable ultralow latency, ultra-reliable, and high throughput services. The disclosed multiple access method includes: allocating resources for a plurality of user terminals according to space and frequency; performing a discrete Fourier transform on a transmission symbol for each unit of the space, the transmission symbol composed of a plurality of sub-symbols and configured to be transmitted according to the allocated space and frequency resources; and applying a frequency filter and a spatial filter on the Fourier transformation result, and wherein the applying of the frequency filter and the spatial filter comprises: selecting a pulse shaping filter according to an arranged position of the allocated frequency resource for each unit of the space and applying the selected pulse shaping filter on a sample representing a result of applying a Fourier transform on the sub-symbol to a frequency domain.

Abstract: The method for predicting a wear amount of a chain pin by using a friction noise according to an embodiment of the present invention predicts a wear amount of a chain pin of a roller chain by using a friction noise while the roller chain is revolved by a driving force of a sprocket. The method includes: sensing a noise around the roller chain by means of a noise sensing unit; separating a friction noise between rollers of the roller chain and teeth of the sprocket from the sensed noise around the roller chain by means of a sound source separation unit; and predicting a wear amount of the chain pin using the separated friction noise between the rollers and the teeth by means of a sound source analysis unit.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a chip selection signal, a command/address signal and a clock signal. The first semiconductor device outputs first external data and a strobe signal during a write operation in a test mode and receives second external data to adjust an output moment of the strobe signal during a read operation in the test mode. The second semiconductor device is synchronized with the strobe signal to latch input data generated from the first external data during the write operation according to the chip selection signal and the command/address signal. The second semiconductor device generates output data from the input data and outputs the output data as the second external data during the read operation according to the chip selection signal and the command/address signal.

Abstract: A memory device may include a clock dividing circuit suitable for generating a plurality of internal clocks by dividing an external clock, a mode decision circuit suitable for determining an operation mode according to an input time point of a read command based on the internal clocks, a clock arranging circuit suitable for arranging the internal clocks in an order determined according to the operation mode, and outputting the arranged clocks as a plurality of data output clocks, and a data arranging circuit suitable for arranging read data according to the operation mode, and outputting the arranged data in response to the data output clocks.