Abstract: Disclosed are an apparatus and a method for LDPC encoding suitable for highly reliable and low latency communication. The disclosed apparatus comprises: a second inner encoding module for outputting parity bits by means of single parity calculations and accumulation device calculations using bit strings outputted from a first inner encoding module; and the first inner encoding module for outputting a part of the parity bits by means of single parity check calculations for the bits output from a second outer module, and for outputting rest of the parity bit strings by means of single parity check calculations and accumulation device calculations, with a part of the parity bits output by the second inner encoding module as an additional input.

Abstract: A semiconductor memory device includes: an internal circuit; a write control circuit suitable for writing write data into the internal circuit based on a write strobe signal during a normal write operation, and writing test data into the internal circuit based on a read strobe signal during a test write operation; and a read control circuit suitable for generating the read strobe signal and outputting the read strobe signal together with read data read from the internal circuit during a normal read operation or a test read operation, and generating the read strobe signal and providing the write control circuit with the read strobe signal during the test write operation.

Abstract: The present application provides a method for a multi-user multi-stream supporting base station transmitting a signal to a terminal. The method comprising: estimating channel information of a first terminal by receiving a reference signal from the first terminal; and by using the estimated channel information, transmitting a plurality of beams to the first terminal based on a non-orthogonal multiple access scheme. When transmitting the plurality of beams to the first terminal based on the non-orthogonal multiple access scheme, a plurality of virtual terminals of the first terminal are generated, and a signal for a first virtual terminal among the plurality of virtual terminals are allocated to a first beam and transmitted, and a signal for a second virtual terminal among the plurality of virtual terminals are allocated to a second beam and transmitted.

Abstract: A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal. The second buffer may generate a second data strobe buffering signal based on the first input signal and a reference xvoltage. The divider circuit may divide the second data strobe buffering signal to generate a divided signal and a divided bar signal. The internal signal generation circuit may be configured to generate a first to fourth data latch timing signals having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided buffering signal.

Abstract: The present application provides a method for a multi-user multi-stream supporting base station transmitting a signal to a terminal. The method comprising: estimating channel information of a first terminal by receiving a reference signal from the first terminal; and by using the estimated channel information, transmitting a plurality of beams to the first terminal based on a non-orthogonal multiple access scheme. When transmitting the plurality of beams to the first terminal based on the non-orthogonal multiple access scheme, a plurality of virtual terminals of the first terminal are generated, and a signal for a first virtual terminal among the plurality of virtual terminals are allocated to a first beam and transmitted, and a signal for a second virtual terminal among the plurality of virtual terminals are allocated to a second beam and transmitted.

Abstract: A memory device includes a plurality of memory cell arrays, a plurality of data transmitters corresponding to the plurality of memory cell arrays, respectively, and suitable for transmitting data read in parallel from the corresponding memory cell arrays, and a test circuit suitable for selecting one data transmitter among the plurality of data transmitters, and sequentially outputting data transmitted in parallel from the selected data transmitter to one data input/output pad among a plurality of data input/output pads, during a test mode.

Abstract: A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal. The second buffer may generate a second data strobe buffering signal based on the first input signal and a reference voltage. The divider circuit may divide the second data strobe buffering signal to generate a divided signal and a divided bar signal. The internal signal generation circuit may be configured to generate a first to fourth data latch timing signals having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided buffering signal.

Abstract: A semiconductor device includes a calibration circuit suitable for generating impedance control codes based on an external resistor coupled to a calibration pad; an individual trimming controller suitable for generating a plurality of individual trimming signals based on test mode signals and group selection signals; and a termination circuit including a plurality of resistor groups, coupled in parallel to a data pad, that are trimmed as a group based on the impedance control codes, each of the plurality of resistor groups being individually trimmed based on a corresponding signal among the plurality of individual trimming signals.

Abstract: A full duplex-type base station for removing signal interference between half duplex-type an uplink terminal and a downlink terminal, includes: a channel estimation unit which estimates channel coefficients between the base station, uplink terminal and downlink terminal; a reception precoding matrix generation unit which generates a reception precoding matrix on the basis of a first code and a channel with the uplink terminal; and a transmission precoding matrix generation unit which generates a transmission precoding matrix on the basis of a second code that is orthogonal to the first code, and a channel with the downlink terminal, wherein the first code is used for generating a transmission signal of the uplink terminal, the second code is used for removing the transmission signal—including the first code—of the uplink terminal, which is received as an interference signal at the time the downlink terminal receives a signal from the base station.

Abstract: A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal. The second buffer may generate a second data strobe buffering signal based on the first input signal and a reference voltage. The divider circuit may divide the second data strobe buffering signal to generate a divided signal and a divided bar signal. The internal signal generation circuit may be configured to generate a first to fourth data latch timing signals having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided buffering signal.

Abstract: A central management server for special communication may include: a spectrum sensing information acquisition unit for acquiring spectrum sensing information from spectrum sensing servers; an OP map generation unit for generating an OP value for each channel if there is an access request from a second layer; and a channel allocation unit configured to allocate a channel based on the OP value to a user terminal of the second layer requesting access if there is an access request from the second layer. The channel allocation unit may allocate a channel corresponding to the highest OP value from among the available channels, if there are available channels unused by both a first layer and a lower-level layer, and may select and allocate a channel unused by the first layer but used by the lower-level layer, if there are no such available channels.

Abstract: A scheduling apparatus and method are disclosed. An embodiment of the invention provides a scheduling apparatus that includes: a scheduling group classification unit that classifies user terminals located within a serving cell of a base station into a multiple number of scheduling groups by using large-scale fading information of the user terminals; a transmission power setting unit that sets the transmission power of the user terminals for each of the classified scheduling groups; a scheduling period setting unit that sets the scheduling period for each of the scheduling groups by determining a resource element usage proportion for each of the scheduling groups based on the data rate of each of the scheduling groups and determining the data rate expected for all user terminals; and a resource element allocation unit that allocates resource elements used for each of the scheduling groups according to each of the determined scheduling periods.

Abstract: A semiconductor device includes a calibration circuit suitable for generating impedance control codes based on an external resistor coupled to a calibration pad; an individual trimming controller suitable for generating a plurality of individual trimming signals based on test mode signals and group selection signals; and a termination circuit including a plurality of resistor groups, coupled in parallel to a data pad, that are trimmed as a group based on the impedance control codes, each of the plurality of resistor groups being individually trimmed based on a corresponding signal among the plurality of individual trimming signals.

Abstract: A central management server for special communication may include: a spectrum sensing information acquisition unit for acquiring spectrum sensing information from spectrum sensing servers; an OP map generation unit for generating an OP value for each channel if there is an access request from a second layer; and a channel allocation unit configured to allocate a channel based on the OP value to a user terminal of the second layer requesting access if there is an access request from the second layer. The channel allocation unit may allocate a channel corresponding to the highest OP value from among the available channels, if there are available channels unused by both a first layer and a lower-level layer, and may select and allocate a channel unused by the first layer but used by the lower-level layer, if there are no such available channels.

Abstract: Disclosed are method and apparatus for enabling multiple access in a wireless communication system that can enable ultralow latency, ultra-reliable, and high throughput services. The disclosed multiple access method includes: allocating resources for a plurality of user terminals according to space and frequency; performing a discrete Fourier transform on a transmission symbol for each unit of the space, the transmission symbol composed of a plurality of sub-symbols and configured to be transmitted according to the allocated space and frequency resources; and applying a frequency filter and a spatial filter on the Fourier transformation result, and wherein the applying of the frequency filter and the spatial filter comprises: selecting a pulse shaping filter according to an arranged position of the allocated frequency resource for each unit of the space and applying the selected pulse shaping filter on a sample representing a result of applying a Fourier transform on the sub-symbol to a frequency domain.

Abstract: Disclosed are an apparatus and a method for LDPC encoding suitable for highly reliable and low latency communication. The disclosed apparatus comprises: a second inner encoding module for outputting parity bits by means of single parity calculations and accumulation device calculations using bit strings outputted from a first inner encoding module; and the first inner encoding module for outputting a part of the parity bits by means of single parity check calculations for the bits output from a second outer module, and for outputting rest of the parity bit strings by means of single parity check calculations and accumulation device calculations, with a part of the parity bits output by the second inner encoding module as an additional input.

Abstract: A semiconductor system includes a controller operatively coupled to a semiconductor device, the controller being suitable in a training mode for receiving an external signal and a first data signal from an external device and for transmitting the received external signal and the first data signal to the semiconductor device; and the semiconductor device being suitable in the training mode for determining a level of a reference voltage in response to the first data signal, and for transmitting a second data signal to the controller by buffering the external signal based on the reference voltage without performing a termination operation during an output period of the second data signal, wherein the controller controls an enable timing of the external signal by receiving the second data signal.

Abstract: A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal. The second buffer may generate a second data strobe buffering signal based on the first input signal and a reference voltage. The divider circuit may divide the second data strobe buffering signal to generate a divided signal and a divided bar signal. The internal signal generation circuit may be configured to generate a first to fourth data latch timing signals having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided buffering signal.

Abstract: Provided is a method and an apparatus for uplink and downlink separated connections, wherein a terminal may establish a downlink cell association with a downlink base station, receive an identifier of an uplink base station providing an uplink from the downlink base station to the terminal through an established downlink, and establish an uplink cell association with the uplink base station using the identifier of the uplink base station, and the downlink base station may select the uplink base station from among base stations in a network based on an uplink reference signal and a bias factor.

Abstract: Disclosed is a downlink signal configuring method and device, and synchronization and cell search method and device using the same in a mobile communication system. A downlink frame has plural symbols into which pilot subcarriers are distributively arranged with respect to time and frequency axes. Initial symbol synchronization and initial frequency synchronization are estimated by using a position at which autocorrelation of a cyclic prefix of a downlink signal and a valid symbol of the downlink is maximized, and cell search and integer-times frequency synchronization are estimated by using pilot subcarriers included in the estimated symbol. Fine symbol synchronization, fine frequency synchronization, and downlink frame synchronization is estimated by using an estimated cell search result.