Abstract: The present disclosure relates to modified homoserine dehydrogenase and a method for producing homoserine or a homoserine-derived L-amino acid using the same.

Abstract: A storage device, including a feature information database configured to store feature information about a memory device; and a machine learning module configured to select a machine learning model from a plurality of machine learning models the corresponding to an operation of the memory device based on the feature information, wherein the memory device is configured to operate according to the selected machine learning model.

Abstract: A nonvolatile memory device capable of minimizing monitoring overhead associated with read disturb is provided. The nonvolatile memory device includes a memory cell array which includes a first cell string comprising a plurality of memory cells connected in series, wherein the plurality of memory cells includes a first monitoring cell, a first memory cell, and a second memory cell, and a row decoder which provides a first read voltage to the first memory cell and a first monitoring voltage to the first monitoring cell when reading the first memory cell among the memory cells and provides the first read voltage to the second memory cell and a second monitoring voltage different from the first monitoring voltage to the first monitoring cell when reading the second memory cell.

Abstract: A variable resistance memory device includes a word line extending in a first direction, a bit line on the word line and extending in a second direction intersecting the first direction, a switching pattern between the bit line and the word line, a phase change pattern between the switching pattern and the word line, and a bottom electrode between the phase change pattern and the word line, wherein the phase change pattern has a bottom area greater than a top area of the bottom electrode, a thickness of the phase change pattern being greater than a thickness of the bottom electrode, and wherein the bottom and top areas are defined in the first and second directions, and the thicknesses are defined in a third direction intersecting the first and second directions.

Abstract: The present disclosure relates to a microorganism for producing an L-amino acid with enhanced activity of ?-glucosidase and a method for producing an L-amino acid using the same. According to the present disclosure, the microorganism of the genus Corynebacterium producing an L-amino acid has enhanced activity of ?-glucosidase, thereby improving L-amino acid production yield. Therefore, the microorganism may be very usefully used for L-amino acid production.

Abstract: A microorganism of the genus Corynebacterium producing L-amino acids, and a method of producing L-amino acids using the same.

Abstract: A capsule buoy type wave energy converter according to an embodiment of the present invention includes a buoy installed on the water surface, and a power generating unit received in the buoy in a sealed manner so as to generate power. The power generating unit may include a generator for generating power, at least one wave actuator for converting bidirectional movement caused by wave power into unidirectional movement, a torque generator for generating torque by the unidirectional movement transmitted from the wave actuator, and an accelerator for accelerating the torque from the torque generator so as to operate the generator.

Abstract: The present disclosure relates to modified homoserine dehydrogenase and a method for producing homoserine or a homoserine-derived L-amino acid using the same.

Abstract: A method of operating a resistive memory device to increase a read margin includes applying a write pulse to a memory cell such that the memory cell is programmed to a target resistance state, and applying a post-write pulse to the memory cell to increase a resistance of the memory cell that is in the target resistance state, the post-write pulse being applied as a single pulse having at least n stepped voltage levels, n being an integer equal to or more than 2, and an n-th stepped voltage level of the post-write pulse is set to be lower than a minimum threshold voltage level of the target resistance state that is changed by an (n?1)-th stepped voltage level of the post-write pulse.

Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction.

Abstract: A variable resistance memory device includes a word line extending in a first direction, a bit line on the word line and extending in a second direction intersecting the first direction, a switching pattern between the bit line and the word line, a phase change pattern between the switching pattern and the word line, and a bottom electrode between the phase change pattern and the word line, wherein the phase change pattern has a bottom area greater than a top area of the bottom electrode, a thickness of the phase change pattern being greater than a thickness of the bottom electrode, and wherein the bottom and top areas are defined in the first and second directions, and the thicknesses are defined in a third direction intersecting the first and second directions.

Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction.

Abstract: A non-volatile memory device includes a substrate, a first electrode on the substrate, a second electrode on the substrate, a selection layer between the first electrode and the second electrode, and a memory layer contacting any one of the first electrode and the second electrode. The first electrode has a first width in a first direction. The second electrode is spaced apart from the first electrode in a second direction perpendicular to the first direction. The second electrode has a second width in the first direction. The selection element layer includes a first doped layer that contacts the first electrode. The first doped layer includes an impurity at a first concentration. The selection element layer includes a second doped layer that contacts the second electrode. The second doped layer includes the impurity at a second concentration lower than the first concentration.

Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality of first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction.

Abstract: A method of manufacturing a semiconductor device includes forming a first gate structure on a substrate, the first gate structure including a gate insulation layer, a gate electrode, and a hard mask sequentially stacked on the substrate, forming a preliminary spacer layer on sidewalls of the first gate structure and the substrate, the preliminary spacer layer including silicon nitride, implanting molecular ions into the preliminary spacer layer to form a spacer layer having a dielectric constant lower than a dielectric constant of the preliminary spacer layer, anisotropically etching the spacer layer to form spacers on the sidewalls of the first gate structure, and forming impurity regions at upper portions of the substrate adjacent to the first gate structure.

Abstract: A method of authenticating a user of an image forming apparatus is provided that includes receiving, at the image forming apparatus, a one-time password (OTP) generating request, generating, at the image forming apparatus, an OTP according to the OTP generating request, receiving, at the image forming apparatus, an authentication request, from the host apparatus, including the OTP, and when the OTP received from the host apparatus matches the OTP generated according to the OTP generating request and absent a condition, approving an access to the image forming apparatus.

Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality of first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction.

Abstract: A system detects Electro Static Discharge (ESD) of an electronic device by sensing a ground voltage of an electronic device, comparing the sensed ground voltage with a predetermined reference voltage and if the sensed ground voltage exceeds the reference voltage, performs at least one predetermined operation of the electronic device.

Abstract: A method of manufacturing a semiconductor device includes forming a first gate structure on a substrate, the first gate structure including a gate insulation layer, a gate electrode, and a hard mask sequentially stacked on the substrate, forming a preliminary spacer layer on sidewalls of the first gate structure and the substrate, the preliminary spacer layer including silicon nitride, implanting molecular ions into the preliminary spacer layer to form a spacer layer having a dielectric constant lower than a dielectric constant of the preliminary spacer layer, anisotropically etching the spacer layer to form spacers on the sidewalls of the first gate structure, and forming impurity regions at upper portions of the substrate adjacent to the first gate structure.

Abstract: An organic light-emitting display device that includes a substrate, first and second electrodes facing each other on the substrate, an organic light-emitting layer between the first and second electrodes, a thin-film encapsulation (TFE) film on the second electrode, a reflection reduction layer on the TFE film, and a refraction adjustment layer between the reflection reduction layer and the organic light-emitting layer.