Abstract: A writing method of a nonvolatile memory device is provided which receiving data, a target time, and a target resistance value; writing the data at a memory cell; calculating a resistance drift coefficient based on resistance values of the memory cell read on at least two times; calculating a resistance value of the memory cell on the target time using the resistance drift coefficient; and determining whether the resistance value calculated satisfies the target resistance value.

Abstract: A method is provided for refreshing a volatile memory. The method includes storing address information about a weak cell row address that is to be refreshed according to a weak cell refresh period that is shorter than a refresh period, performing a counting operation for generating a refresh row address, comparing the refresh row address with the address information, refreshing the weak cell row address when a result of the comparison shows that the refresh row address and the weak cell row address of the address information coincide with each other, changing the weak cell row address by changing a pointer of the address information, and refreshing the changed weak cell row address according to the weak cell refresh period.

Abstract: A semiconductor memory device includes: a normal memory cell block including a first plurality of memory cells; a redundancy memory cell block including a second plurality of memory cells and configured for use in replacing memory cells of the normal memory cell block; a weak cell information storage configured to store information regarding weak memory cells in the normal and redundancy memory cell blocks; and a refresh control circuit configured to control a refresh rate of memory cells in the normal and redundancy memory cell blocks based on the information regarding weak memory cells in the weak cell information storage. The weak memory cells in the normal and redundancy memory cell blocks are refreshed at least once more than other memory cells in the normal and redundancy memory cell blocks during a refresh cycle.

Abstract: A refresh leveraging driving method is provided which includes deciding a unit of word lines to be driven at a refresh leveraging operation to be the same as a redundancy repair row unit setting a lower row address of an input refresh leveraging address corresponding to the decided refresh leveraging row driving unit to a don't care state; and internally generating the don't care lower row address of the refresh leveraging address to drive word lines according to a combined refresh leveraging address.

Abstract: A system detects Electro Static Discharge (ESD) of an electronic device by sensing a ground voltage of an electronic device, comparing the sensed ground voltage with a predetermined reference voltage and if the sensed ground voltage exceeds the reference voltage, performs at least one predetermined operation of the electronic device.

Abstract: A method is provided for refreshing a volatile memory. The method includes storing address information about a weak cell row address that is to be refreshed according to a weak cell refresh period that is shorter than a refresh period, performing a counting operation for generating a refresh row address, comparing the refresh row address with the address information, refreshing the weak cell row address when a result of the comparison shows that the refresh row address and the weak cell row address of the address information coincide with each other, changing the weak cell row address by changing a pointer of the address information, and refreshing the changed weak cell row address according to the weak cell refresh period.

Abstract: A method of authenticating a user of an image forming apparatus is provided that includes receiving, at the image forming apparatus, a one-time password (OTP) generating request, generating, at the image forming apparatus, an OTP according to the OTP generating request, receiving, at the image forming apparatus, an authentication request, from the host apparatus, including the OTP, and when the OTP received from the host apparatus matches the OTP generated according to the OTP generating request and absent a condition, approving an access to the image forming apparatus.

Abstract: The present invention relates to a microorganism with improved production of 5?-xanthosine monophosphate and 5?-guanine monophosphate, and more specifically, to a Corynebacterium sp. microorganism having increased proline dehydrogenase activity compared with an intrinsic activity thereof, a method for producing 5?-xanthosine monophosphate or 5?-guanine monophosphate from the culture medium obtained by culturing the transformed microorganism, and a use of the microorganism for production of 5?-xanthosine monophosphate or 5?-guanine monophosphate.

Abstract: A semiconductor memory device includes: a normal memory cell block including a first plurality of memory cells; a redundancy memory cell block including a second plurality of memory cells and configured for use in replacing memory cells of the normal memory cell block; a weak cell information storage configured to store information regarding weak memory cells in the normal and redundancy memory cell blocks; and a refresh control circuit configured to control a refresh rate of memory cells in the normal and redundancy memory cell blocks based on the information regarding weak memory cells in the weak cell information storage. The weak memory cells in the normal and redundancy memory cell blocks are refreshed at least once more than other memory cells in the normal and redundancy memory cell blocks during a refresh cycle.

Abstract: A writing method of a nonvolatile memory device is provided which receiving data, a target time, and a target resistance value; writing the data at a memory cell; calculating a resistance drift coefficient based on resistance values of the memory cell read on at least two times; calculating a resistance value of the memory cell on the target time using the resistance drift coefficient; and determining whether the resistance value calculated satisfies the target resistance value.

Abstract: A refresh leveraging driving method is provided which includes deciding a unit of word lines to be driven at a refresh leveraging operation to be the same as a redundancy repair row unit setting a lower row address of an input refresh leveraging address corresponding to the decided refresh leveraging row driving unit to a don't care state; and internally generating the don't care lower row address of the refresh leveraging address to drive word lines according to a combined refresh leveraging address.

Abstract: The present invention relates to a microorganism with improved production of 5?-xanthosine monophosphate and 5?-guanine monophosphate, and more specifically, to a Corynebacterium sp. microorganism having increased proline dehydrogenase activity compared with an intrinsic activity thereof, a method for producing 5?-xanthosine monophosphate or 5?-guanine monophosphate from the culture medium obtained by culturing the transformed microorganism, and a use of the microorganism for production of 5?-xanthosine monophosphate or 5?-guanine monophosphate.

Abstract: A semiconductor device employing a transistor having a recessed channel region and a method of fabricating the same is disclosed. A semiconductor substrate has an active region. A trench structure is defined within the active region. The trench structure includes an upper trench region adjacent to a surface of the active region, a lower trench region and a buffer trench region interposed between the upper trench region and the lower trench region. A width of the lower trench region may be greater than a width of the upper trench region. An inner wall of the trench structure may include a convex region interposed between the upper trench region and the buffer trench region and another convex region interposed between the buffer trench region and the lower trench region. A gate electrode is disposed in the trench structure. A gate dielectric layer is interposed between the gate electrode and the trench structure.

Abstract: Memory devices include a row decoder, a first variable resistance memory cell connected to a first bit line and connected to the row decoder by a word line and a second variable resistance memory cell connected to a second bit line and connected to the row decoder by the word line. The memory devices further include a bit line select circuit coupled to the first and second bit lines and configured to compensate for a difference in word line resistance between the row decoder and the respective first and second memory cells. In some embodiments, the bit line select circuit includes first and second transistors configured to selective respective ones of the first and second bit lines and the first and second transistors have different resistances that compensate for the difference in word line resistance.

Abstract: A variable resistance memory device may include first and second memory cells connected to different lengths of bit lines, respectively, and a select circuit, configured to select the first and second memory cells, which is connected to the first and second memory cells through word lines. The select circuit is configured to compensate for a difference of resistances in the different of the lengths of the bit lines.

Abstract: Memory devices include a row decoder, a first variable resistance memory cell connected to a first bit line and connected to the row decoder by a word line and a second variable resistance memory cell connected to a second bit line and connected to the row decoder by the word line. The memory devices further include a bit line select circuit coupled to the first and second bit lines and configured to compensate for a difference in word line resistance between the row decoder and the respective first and second memory cells. In some embodiments, the bit line select circuit includes first and second transistors configured to selective respective ones of the first and second bit lines and the first and second transistors have different resistances that compensate for the difference in word line resistance.

Abstract: Provided is a variable resistance memory device. The variable resistance memory device may include first and second memory cells connected to different lengths of bit lines, respectively, and a select circuit, configured to select the first and second memory cells, which is connected to the first and second memory cells through word lines. The select circuit is configured to compensate for a difference of resistances in the different of the lengths of the bit lines.

Abstract: A shared key management method for a Supervisory Control And Data Acquisition (SCADA) system in which a master terminal unit (MTU), a plurality of sub master terminal units (SUB-MTUs), and a plurality of remote terminal units (RTUs) are configured in a sequential hierarchy, is provided.

Abstract: An integrated circuit memory cell includes a substrate having a first semiconductor region of first conductivity type (e.g., N-type) therein, which may define a portion of a word line within the substrate. An electrically insulating layer is provided on the substrate. The electrically insulating layer has an opening therein that extends opposite a recess in the first semiconductor region. A first insulating spacer is provided on a sidewall of the recess in the first semiconductor region. A diode is provided in the opening. The diode has a first terminal electrically coupled to a bottom of the recess in the first semiconductor region. A variable resistivity material region (e.g., phase-changeable material region) is also provided. The variable resistivity material region is electrically coupled to a second terminal of the diode.

Abstract: A method of fabricating a semiconductor memory device having a self-aligned electrode is provided. An interlayer insulating layer having a contact hole is formed on a substrate. A phase change pattern partially filling the contact hole is formed. A bit line which includes a bit extension self-aligned to the phase change pattern and crosses over the interlayer insulating layer is formed. The bit extension may extend in the contact hole on the phase change pattern. The bit extension contacts the phase change pattern.