Abstract: A spatial disturbance that occurs when an access is concentrated in a specific memory area in a volatile semiconductor memory like DRAM is properly solved by a memory controller. The memory controller includes a concentration access detection part generating a concentration access detection signal when an address for accessing a specific memory area among memory areas of volatile semiconductor memory is concentratedly received. In the case that the concentration access detection signal is generated, the memory controller includes a controller for easing or preventing corruption of data which memory cells of the specific memory area and/or memory cells of memory areas adjacent to the specific memory area hold.

Abstract: A memory device is provided. The memory device comprises a memory cell array configured to store data, a command decoder configured to receive a command from the exterior to generate a first memory cell control signal, a PIM (Processor In Memory) block configured to generate a second memory cell control signal including a command for performing an internal processing operation on the basis of instructions stored therein and perform an internal processing operation on the basis of the second memory cell control signal, and an operating mode multiplexer configured to output any one of the first memory cell control signal and the second memory cell control signal and provide it to the memory cell array.

Abstract: A neural network device including a convolution static random access memory (SRAM) configured to output a first operation value and a second operation value 1. An accumulation peripheral operator configured to perform an accumulation peripheral operation on the first and the second operation values, a multiplexer array configured to select and output an output value according to a selection signal, a diagonal accumulation SRAM configured to perform a bitwise accumulation of variable weight values and a spatial-wise accumulation operation on an input, a diagonal movement logic, and an addition array operator configured to perform an addition operation of output values of the diagonal movement logic subsequent to a shift operation, the multiplexer array selects any one of an output value of the accumulation peripheral operator and an output value of the addition array operator according to the selection signal and outputs the selected output value to the diagonal accumulation SRAM.

Abstract: A spatial disturbance that occurs when an access is concentrated in a specific memory area in a volatile semiconductor memory like DRAM is properly solved by a memory controller. The memory controller includes a concentration access detection part generating a concentration access detection signal when an address for accessing a specific memory area among memory areas of volatile semiconductor memory is concentratedly received. In the case that the concentration access detection signal is generated, the memory controller includes a controller for easing or preventing corruption of data which memory cells of the specific memory area and/or memory cells of memory areas adjacent to the specific memory area hold.

Abstract: An integrated circuit device includes a stack of integrated circuit memory dies having a plurality of through-substrate vias (TSVs) extending therethrough, and a buffer die electrically coupled to the plurality of TSVs. The buffer die includes a test interface circuit, which is configured to: (i) generate a plurality of internal test signals, which are synchronized with a second clock signal having a second frequency, from at least one control code, and from a plurality of external test signals, which are synchronized with a first clock signal having a first frequency less than the second frequency, and (ii) provide the plurality of internal test signals to at least one of the memory dies in said stack during a first test mode. The second frequency may be greater than three (3) times the first frequency.

Abstract: A spatial disturbance that occurs when an access is concentrated in a specific memory area in a volatile semiconductor memory like DRAM is properly solved by a memory controller. The memory controller includes a concentration access detection part generating a concentration access detection signal when an address for accessing a specific memory area among memory areas of volatile semiconductor memory is concentratedly received. In the case that the concentration access detection signal is generated, the memory controller includes a controller for easing or preventing corruption of data which memory cells of the specific memory area and/or memory cells of memory areas adjacent to the specific memory area hold.

Abstract: Semiconductor memory device includes a memory cell array and an interface circuit including an ECC engine. The memory cell array includes a normal cell region and a parity cell region including a first sub parity region and a second sub parity region. The interface circuit receives main data and sub data comprising external parity or a data mask signal, generates a flag signal based on mask bits of the data mask signal, performs ECC encoding operation on the main data in response to an operation mode and the flag signal, stores the main data in the normal cell region, stores either the external parity or the flag signal in the second sub parity region in response to the operation mode, performs an ECC decoding operation on the main data read from the normal cell region in response to the operation mode and the flag signal.

Abstract: A semiconductor memory device which includes a memory cell array, an error injection register set, a data input buffer, a write data generator, and control logic. The error injection register set stores an error bit set, including at least one error bit, based on a first command. The error bit set is associated with a data set to be written in the memory cell array. The data input buffer stores the data set to be written in the memory cell array based on a second command. The write data generator generates a write data set to be written in the memory cell array based on the data set and the error bit set. The control logic controls the error injection register set and the data input buffer.

Abstract: An integrated circuit device includes a stack of integrated circuit memory dies having a plurality of through-substrate vias (TSVs) extending therethrough, and a buffer die electrically coupled to the plurality of TSVs. The buffer die includes a test interface circuit, which is configured to: (i) generate a plurality of internal test signals, which are synchronized with a second clock signal having a second frequency, from at least one control code, and from a plurality of external test signals, which are synchronized with a first clock signal having a first frequency less than the second frequency, and (ii) provide the plurality of internal test signals to at least one of the memory dies in said stack during a first test mode. The second frequency may be greater than three (3) times the first frequency.

Abstract: A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.

Abstract: A memory device can include a plurality of memory banks coupled to an input/output bus and a memory controller coupled to the plurality of memory banks. The memory controller can be configured to control operations of the plurality of memory banks, where each of the plurality of memory banks can include a bank array including a plurality of memory cells configured to store data, a latch circuit coupled to the input/output bus, where the latch circuit can be configured to store target data received via the input/output bus to provide stored target data, and a comparison circuit coupled to the latch circuit, where the comparison circuit can be configured to compare stored data output by the bank array with the stored target data to provide result data to the memory controller.

Abstract: Semiconductor memory device includes a memory cell array and an interface circuit including an ECC engine. The memory cell array includes a normal cell region and a parity cell region including a first sub parity region and a second sub parity region. The interface circuit receives main data and sub data comprising external parity or a data mask signal, generates a flag signal based on mask bits of the data mask signal, performs ECC encoding operation on the main data in response to an operation mode and the flag signal, stores the main data in the normal cell region, stores either the external parity or the flag signal in the second sub parity region in response to the operation mode, performs an ECC decoding operation on the main data read from the normal cell region in response to the operation mode and the flag signal.

Abstract: A memory cell array may include a normal cell array and a spare cell array, the normal cell array having a plurality of normal memory cells connected to normal lines and the spare memory cell array having a plurality of spare memory cells connected to spare lines configured to replace a failed normal memory cell with a spare memory cell. A spare line address encoding circuit may be configured to generate a spare line address which encodes spare line enable signals being applied when a spare line replacing a normal line is activated to indicate a physical location of the spare line being activated. A spare line adjacent address generator may be configured to generate spare line adjacent address based on the spare line address, and to activate spare lines physically adjacent to the activated spare line.

Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Abstract: A memory device can include a plurality of memory banks coupled to an input/output bus and a memory controller coupled to the plurality of memory banks. The memory controller can be configured to control operations of the plurality of memory banks, where each of the plurality of memory banks can include a bank array including a plurality of memory cells configured to store data, a latch circuit coupled to the input/output bus, where the latch circuit can be configured to store target data received via the input/output bus to provide stored target data, and a comparison circuit coupled to the latch circuit, where the comparison circuit can be configured to compare stored data output by the bank array with the stored target data to provide result data to the memory controller.

Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.

Abstract: A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.

Abstract: A semiconductor memory device which includes a memory cell array, an error injection register set, a data input buffer, a write data generator, and control logic. The error injection register set stores an error bit set, including at least one error bit, based on a first command. The error bit set is associated with a data set to be written in the memory cell array. The data input buffer stores the data set to be written in the memory cell array based on a second command. The write data generator generates a write data set to be written in the memory cell array based on the data set and the error bit set. The control logic controls the error injection register set and the data input buffer.

Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.