Abstract: A method of storing data in a storage medium of a data storage device comprises storing input data in the storage medium, and reading the input data from the storage medium and compressing the read data during a background operation of the data storage device.

Abstract: An embedded multimedia card (eMMC) includes a clock channel receiving a clock from a host, a complementary clock channel receiving a complementary clock from the host, a command/response channel exchanging commands/responses with the host, a plurality of data channels exchanging data between the host and the eMMC, a return clock channel sending a return clock to the host synchronously with data, a complementary return clock channel sending a complementary return clock to the host, and a reference voltage channel that either receives a reference voltage from the host or communicates a reference voltage to the host.

Abstract: An embedded multimedia card (eMMC) is provided. The eMMC includes a clock channel receiving a clock output from a host, data channels receiving data signals from the host, and a command channel receiving a SWITCH command including delay offset values from the host so as to adjust a delay of at least one of the data signals, which are received, in response to the delay offset values.

Abstract: A method of operating a data compression device includes analyzing data using an analyzer and generating a result of the analysis, while the data is buffered by an input buffer, and selectively compressing the buffered data according to the result of the analysis. A data compression device includes a data pattern analyzer configured to analyze data transmitted to an input buffer, and generate an analysis code based on the analysis of the data; and a data compression manager configured to selectively compress the data in the input buffer based on the analysis code.

Abstract: A method of encoding multi-bit level data includes: determining a range of an error pattern generated according to a transmission symbol, encoding an M-bit level of a P-bit level corresponding to the transmission symbol based on the range of the error pattern, and excluding encoding of a P-M bit level of the P-bit level. The variable P is a natural number of a value at least two, and the variable M is a natural number less than P.

Abstract: A method of determining a read voltage of a memory device comprises performing a plurality of read operations with respective different read voltages on a first group of storage regions of the memory device using a first error correction rate, wherein the plurality of read operations are performed to distinguish between a pair of adjacent logic states of memory cells in the first group of storage regions, detecting a read voltage level, among the different read voltages, at which a minimum number of erroneous bits is generated in the at least one read operation, and determining a read voltage for a second group of storage regions to which a second error correction rate is applied, based on the detected read voltage level, wherein the first error correction rate is higher than the second error correction rate.

Abstract: An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N.

Abstract: At least one example embodiment discloses a method of compressing data in a storage device. The method includes determining a codeword length of a symbol using a first table indicating a relationship between a number of occurrences of the symbol in received data and the codeword length, determining a codeword having the codeword length for the symbol, and generating compressed data of the received data, the generating including converting the symbol into the codeword.

Abstract: An error correction apparatus, a method thereof, and a memory device including the apparatus are provided. The error correction apparatus may include: a determination unit configured to determine whether a number of errors in a read word being read and extracted from a multi-level cell (MLC) exists in an error correcting capability range; a read voltage control unit configured to either increase or decrease a read voltage applied to the MLC when the number of errors in the read word is outside the error correcting capability range; and a codeword determination unit configured to analyze a bit error based on the increase or decrease of the read voltage, and to select a codeword corresponding to the analyzed bit error based on a selected read error pattern. Through this, it may be possible to efficiently correct a read error that occurs when the data of the memory device is maintained for a long time.

Abstract: A method of reading data in a non-volatile memory device. The method includes reading a plurality of memory cells of a first page in a memory cell array using a first read level, reading a plurality of memory cells of a second page adjacent to the memory cells of the first page using a second read level, determining whether a state of each memory cell of the first page has been changed based on the first read level to verify a threshold voltage of each memory cell of the second page based on the second read level, and revising the state of each memory cell of the second page according to a result of the determination.

Abstract: Memory devices and/or methods of storing memory data bits are provided. A memory device includes a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and/or methods, it is possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability.

Abstract: A unit pixel of a photo detecting apparatus includes a photogate, a transfer gate and a floating diffusion region. The photogate includes a junction gate extending in a first direction and a plurality of finger gates extending from the junction gate in a second direction substantially perpendicular to the first direction. The transfer gate is formed adjacent to the junction gate. The floating diffusion region is formed adjacent to the first transfer gate.

Abstract: A non-volatile memory device includes a memory cell array including a plurality of multi-level cells each storing data corresponding to one of a plurality of states of a first group of states, and a control circuit. The control circuit is configured to program data corresponding to one of the plurality of states in a first multi-level cell according to a first verify voltage level of a first group of verify voltage levels, and to control the first multi-level cell to be re-programmed to one of a plurality of states of a second group of states according to a first verify voltage level of a second group of verify voltage levels. Each voltage level of the second group of verify voltage levels has a higher level than the verify voltage levels of the first group of verify voltage levels.

Abstract: Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.

Abstract: An image sensor comprises a photoelectric conversion element receiving light to accumulate photocharges, and a wavelength conversion layer formed above the photoelectric conversion element to convert light within a first wavelength band into light within a second wavelength band shorter than the first wavelength band and supply the converted light to the photoelectric conversion element.

Abstract: A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.

Abstract: The memory device selects any one of a first memory cell and a second memory cell based on a number of times that the first memory cell is erased, an elapsed time after the first memory cell is erased, a number of times that the second memory cell is erased, and an elapsed time after the second memory cell is erased, and program data in the selected memory cell. The memory device may improve distribution of threshold voltage of memory cells and endurance of the memory cells.

Abstract: Disclosed is a method of controlling a nonvolatile memory device which includes programming data in a user data area of the nonvolatile memory device and state information on logical states of the data in a meta area of the nonvolatile memory device; and adjusting levels of a plurality of read voltages using the state information to read the data from the user data area using the plurality of read voltages having the adjusted levels.

Abstract: A method of operating a nonvolatile memory device comprises defining a bit ordering for a plurality of n-bit (n>2) multi-level cells such that bit-reading numbers associated with different pages of the n-bit multi-level cells are substantially equalized, wherein the bit ordering assigns at least one bit “0” to an erased state of the n-bit multi-level cells, and programming n-bit data into each of the n-bit multi-level cells according to the bit ordering.

Abstract: A data compression method includes; generating compressed data from raw data having a normal size, defining a super page for a memory having a super size greater than the normal size, selecting a compressed data set from among the compressed data having a compression ratio less than a reference compression ratio ranging between 0.5 and 1.0, and storing the compressed data set in the memory using the super page.