Patents by Inventor Kyoung Moo Harr
Kyoung Moo Harr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10741461Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip. In the fan-out semiconductor package, step portions of the protrusion bumps may be removed.Type: GrantFiled: July 16, 2018Date of Patent: August 11, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyoung Joon Kim, Kyung Seob Oh, Kyoung Moo Harr
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Patent number: 10622322Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, the semiconductor chip having an active surface with connection pads disposed thereon and the semiconductor chip having an inactive surface opposing the active surface, an encapsulant, and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, wherein the first connection member and the second connection member include redistribution layers electrically connected to the connection pads, wherein the semiconductor chip includes a first passivation layer disposed on the active surface and the semiconductor chip includes a second passivation layer disposed on the first passivation layer, and wherein the redistribution layer of the second connection member is directly formed on one surface of the second passivation layer and extends onto one surface of the first connection member.Type: GrantFiled: June 23, 2017Date of Patent: April 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyoung Joon Kim, Doo Hwan Lee, Kyoung Moo Harr, Kyung Seob Oh
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Publication number: 20200027833Abstract: A semiconductor package includes: a semiconductor chip; an encapsulant covering at least a portion of the semiconductor chip; a connection structure disposed on an active surface of the semiconductor chip, and including one or more redistribution layers electrically connected to a connection pad of the semiconductor chip; a surface treatment layer disposed on a surface of a lowermost redistribution layer, among one or more redistribution layers, of the connection structure; and a passivation layer disposed on the connection structure, covering at least a portion of each of the lowermost redistribution layer and the surface treatment layer, and having an opening exposing at least a portion of the surface treatment layer. A surface on which the surface treatment layer is disposed, of the lowermost redistribution layer, has a surface roughness greater than that of an opposite surface, and the surface treatment layer has irregularities along the surface roughness.Type: ApplicationFiled: March 5, 2019Publication date: January 23, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hyun Lee, Jung Gon Choi, Kyoung Moo Harr
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Patent number: 10388614Abstract: The present disclosure relates to a fan-out semiconductor package including a frame having a through hole, a semiconductor chip disposed in the through hole, a first encapsulant disposed in a space between the frame and the semiconductor chip, a second encapsulant disposed on one sides of the frame and the semiconductor chip, and a redistribution layer disposed on the other sides of the frame and the semiconductor chip, and a method of manufacturing the same. The first encapsulant and the second encapsulant may include different materials.Type: GrantFiled: March 6, 2018Date of Patent: August 20, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hyun Lee, Kyoung Moo Harr, Seung Yeop Kook, Ji Hoon Kim, Young Gwan Ko
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Patent number: 10224288Abstract: A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.Type: GrantFiled: October 9, 2017Date of Patent: March 5, 2019Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Kyung Seob Oh, Kyoung Moo Harr, Doo Hwan Lee, Seung Chul Oh, Hyoung Joon Kim, Yoon Suk Cho
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Patent number: 10211149Abstract: A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on an active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip. The redistribution layer includes a line pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width, greater than the first line width, a fan-in region is a projected surface of the semiconductor chip projected in a direction perpendicular to the active surface, a fan-out region is a region surrounding the fan-in region, and the second line portion at least passes through a boundary between the fan-in region and the fan-out region.Type: GrantFiled: September 20, 2017Date of Patent: February 19, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Kyoung Moo Harr, Kyung Seob Oh, Hyoung Joon Kim
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Patent number: 10170382Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip. In the fan-out semiconductor package, step portions of the protrusion bumps may be removed.Type: GrantFiled: June 26, 2017Date of Patent: January 1, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Hyoung Joon Kim, Kyung Seob Oh, Kyoung Moo Harr
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Patent number: 10154594Abstract: A printed circuit board including a circuit board having a cavity between an upper surface of the circuit board and a lower surface of the circuit board that are substantially parallel to each other, and a connection board including insulating layers substantially parallel with metal layers, the metal layers including metal patterns. The connection board is disposed in the cavity with the insulating layers and the metal layers of the connection board substantially perpendicular to the upper and lower surfaces of the circuit board.Type: GrantFiled: September 30, 2015Date of Patent: December 11, 2018Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jeong-Ho Lee, Young-Do Kweon, Hyoung-Joon Kim, Kyoung-Moo Harr, Kyung-Seob Oh
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Publication number: 20180323119Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip. In the fan-out semiconductor package, step portions of the protrusion bumps may be removed.Type: ApplicationFiled: July 16, 2018Publication date: November 8, 2018Inventors: Hyoung Joon KIM, Kyung Seob OH, Kyoung Moo HARR
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Patent number: 10062652Abstract: The present disclosure relates to a fan-out semiconductor package including a frame having a through hole, a semiconductor chip disposed in the through hole, a first encapsulant disposed in a space between the frame and the semiconductor chip, a second encapsulant disposed on one sides of the frame and the semiconductor chip, and a redistribution layer disposed on the other sides of the frame and the semiconductor chip, and a method of manufacturing the same. The first encapsulant and the second encapsulant may include different materials.Type: GrantFiled: November 15, 2016Date of Patent: August 28, 2018Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Ji Hyun Lee, Kyoung Moo Harr, Seung Yeop Kook, Ji Hoon Kim, Young Gwan Ko
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Publication number: 20180240751Abstract: A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on an active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip. The redistribution layer includes a line pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width, greater than the first line width, a fan-in region is a projected surface of the semiconductor chip projected in a direction perpendicular to the active surface, a fan-out region is a region surrounding the fan-in region, and the second line portion at least passes through a boundary between the fan-in region and the fan-out region.Type: ApplicationFiled: September 20, 2017Publication date: August 23, 2018Inventors: Kyoung Moo HARR, Kyung Seob OH, Hyoung Joon KIM
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Publication number: 20180226350Abstract: A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a connection member disposed on the active surface of the semiconductor chip. The connection member includes a plurality of insulating layers, a plurality of redistribution layers disposed on the plurality of insulating layers, respectively, and a plurality of via layers penetrating through the plurality of insulating layers, respectively, and at least two of the plurality of insulating layers or at least two of the plurality of via layers have different thicknesses.Type: ApplicationFiled: August 29, 2017Publication date: August 9, 2018Inventors: Ji Hyun LEE, Hyoung Joon KIM, Kyoung Moo HARR
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Patent number: 10043758Abstract: A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a connection member disposed on the active surface of the semiconductor chip. The connection member includes a plurality of insulating layers, a plurality of redistribution layers disposed on the plurality of insulating layers, respectively, and a plurality of via layers penetrating through the plurality of insulating layers, respectively, and at least two of the plurality of insulating layers or at least two of the plurality of via layers have different thicknesses.Type: GrantFiled: August 29, 2017Date of Patent: August 7, 2018Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Ji Hyun Lee, Hyoung Joon Kim, Kyoung Moo Harr
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Publication number: 20180197827Abstract: The present disclosure relates to a fan-out semiconductor package including a frame having a through hole, a semiconductor chip disposed in the through hole, a first encapsulant disposed in a space between the frame and the semiconductor chip, a second encapsulant disposed on one sides of the frame and the semiconductor chip, and a redistribution layer disposed on the other sides of the frame and the semiconductor chip, and a method of manufacturing the same. The first encapsulant and the second encapsulant may include different materials.Type: ApplicationFiled: March 6, 2018Publication date: July 12, 2018Inventors: Ji Hyun LEE, Kyoung Moo HARR, Seung Yeop KOOK, Ji Hoon KIM, Young Gwan KO
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Publication number: 20180122759Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, the semiconductor chip having an active surface with connection pads disposed thereon and the semiconductor chip having an inactive surface opposing the active surface, an encapsulant, and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, wherein the first connection member and the second connection member include redistribution layers electrically connected to the connection pads, wherein the semiconductor chip includes a first passivation layer disposed on the active surface and the semiconductor chip includes a second passivation layer disposed on the first passivation layer, and wherein the redistribution layer of the second connection member is directly formed on one surface of the second passivation layer and extends onto one surface of the first connection member.Type: ApplicationFiled: June 23, 2017Publication date: May 3, 2018Inventors: Hyoung Joon KIM, Doo Hwan LEE, Kyoung Moo HARR, Kyung Seob OH
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Publication number: 20180090402Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip. In the fan-out semiconductor package, step portions of the protrusion bumps may be removed.Type: ApplicationFiled: June 26, 2017Publication date: March 29, 2018Inventors: Hyoung Joon KIM, Kyung Seob OH, Kyoung Moo HARR
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Patent number: 9905526Abstract: An electronic component package includes a redistribution layer, an electronic component disposed on the redistribution layer, and an encapsulant encapsulating the electronic component. The electronic component has a trench formed in one side thereof.Type: GrantFiled: June 24, 2016Date of Patent: February 27, 2018Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Kyoung Moo Harr, Ji Hoon Kim, Kyung Seob Oh, Sun Ho Kim
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Publication number: 20180033733Abstract: A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.Type: ApplicationFiled: October 9, 2017Publication date: February 1, 2018Inventors: Kyung Seob OH, Kyoung Moo HARR, Doo Hwan LEE, Seung Chul OH, Hyoung Joon KIM, Yoon Suk CHO
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Patent number: 9881873Abstract: A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.Type: GrantFiled: January 31, 2017Date of Patent: January 30, 2018Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Kyung Seob Oh, Kyoung Moo Harr, Doo Hwan Lee, Seung Chul Oh, Hyoung Joon Kim, Yoon Suk Cho
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Publication number: 20170365558Abstract: A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.Type: ApplicationFiled: January 31, 2017Publication date: December 21, 2017Inventors: Kyung Seob OH, Kyoung Moo HARR, Doo Hwan LEE, Seung Chul OH, Hyoung Joon KIM, Yoon Suk CHO