Patents by Inventor Kyoung Moo Harr

Kyoung Moo Harr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170271272
    Abstract: The present disclosure relates to a fan-out semiconductor package including a frame having a through hole, a semiconductor chip disposed in the through hole, a first encapsulant disposed in a space between the frame and the semiconductor chip, a second encapsulant disposed on one sides of the frame and the semiconductor chip, and a redistribution layer disposed on the other sides of the frame and the semiconductor chip, and a method of manufacturing the same. The first encapsulant and the second encapsulant may include different materials.
    Type: Application
    Filed: November 15, 2016
    Publication date: September 21, 2017
    Inventors: Ji Hyun LEE, Kyoung Moo HARR, Seung Yeop KOOK, Ji Hoon KIM, Young Gwan KO
  • Publication number: 20170125318
    Abstract: An electronic component package includes a redistribution layer, an electronic component disposed on the redistribution layer, and an encapsulant encapsulating the electronic component. The electronic component has a trench formed in one side thereof.
    Type: Application
    Filed: June 24, 2016
    Publication date: May 4, 2017
    Inventors: Kyoung Moo HARR, Ji Hoon KIM, Kyung Seob OH, Sun Ho KIM
  • Publication number: 20160316557
    Abstract: A printed circuit board, a method of manufacturing a printed circuit board, and an electronic component module including a printed circuit board are provided. The printed circuit board includes a circuit board having a cavity, and a connection board including metal patterns, the connection board disposed in the cavity with the metal patterns disposed substantially vertically in the circuit board.
    Type: Application
    Filed: September 30, 2015
    Publication date: October 27, 2016
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jeong-Ho LEE, Young-Do KWEON, Hyoung-Joon KIM, Kyoung-Moo HARR, Kyung-Seob OH
  • Publication number: 20160198568
    Abstract: A printed circuit board includes a first insulating layer including a first circuit pattern, a second insulating layer including a second circuit pattern, and a dummy pattern disposed in the first insulating layer and the second insulating layer, in which the first and second insulating layers are made of different materials. An electronic component module includes a printed circuit board and an electronic component mounted on the printed circuit board.
    Type: Application
    Filed: January 4, 2016
    Publication date: July 7, 2016
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Mi Jin PARK, Kyoung Moo HARR, Seung Wan SHIN
  • Patent number: 8957319
    Abstract: Disclosed herein is a method for removing a seed layer in manufacturing a printed circuit board, the method including: forming a photo resist layer on a printed circuit board having a seed layer formed on a surface thereof; removing the photo resist layer according to a predetermined pattern; forming a plating layer for a circuit on the predetermined pattern from which the photo resist layer is removed; exposing the seed layer by removing the photo resist layer around the plating layer; forming a corrosion layer on surfaces of the seed layer and the plating layer by performing a chemical reaction of the substrate from which the seed layer is exposed in a reactor in which a predetermined gas is filled; and removing the seed layer by irradiating a laser on the corrosion layer to remove the corrosion layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 17, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sung Han, Yoon Su Kim, Kyoung Moo Harr, Kyung Seob Oh, Kyung Suk Shim, Du Sung Jung
  • Publication number: 20150000958
    Abstract: The present invention discloses a printed circuit board including a lower wiring layer, an insulating layer which buries the lower wiring layer, and an upper wiring layer formed on the insulating layer to improve reliability of interlayer electrical connection between the wiring layers, wherein the interlayer connection between the upper wiring layer and the lower wiring layer is performed by a via electrode which is provided between the upper wiring layer and the lower wiring layer and has an upper surface bonded to the upper wiring layer and a lower surface bonded to the lower wiring layer, wherein the lower surface of the via electrode is larger than the upper surface thereof.
    Type: Application
    Filed: November 7, 2013
    Publication date: January 1, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kyoung Moo HARR, Hyung Jin JEON, Jin Gu KIM, Young Jae LEE, Young Do KWEON, Chang Bae LEE
  • Publication number: 20140186651
    Abstract: Disclosed herein are a printed circuit board having a copper plated layer with an anchor shaped surface and roughness by forming the copper plated layer having an anisotropic crystalline orientation structure using a plating inhibitor at the time of forming the copper plated layer serving as a circuit wiring and using composite gas plasma and a dilute acid solution, and a method of manufacturing the same.
    Type: Application
    Filed: December 24, 2013
    Publication date: July 3, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sung Han, Yoon Su Kim, Doo Sung Jung, Eun Jung Lim, Kyoung Moo Harr, Kyung Suk Shim, Kyung Seob Oh
  • Publication number: 20140076619
    Abstract: Disclosed herein is a method for removing a seed layer in manufacturing a printed circuit board, the method including: forming a photo resist layer on a printed circuit board having a seed layer formed on a surface thereof; removing the photo resist layer according to a predetermined pattern; forming a plating layer for a circuit on the predetermined pattern from which the photo resist layer is removed; exposing the seed layer by removing the photo resist layer around the plating layer; forming a corrosion layer on surfaces of the seed layer and the plating layer by performing a chemical reaction of the substrate from which the seed layer is exposed in a reactor in which a predetermined gas is filled; and removing the seed layer by irradiating a laser on the corrosion layer to remove the corrosion layer.
    Type: Application
    Filed: March 14, 2013
    Publication date: March 20, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sung Han, Yoon Su Kim, Kyoung Moo Harr, Kyung Seob Oh, Kyung Suk Shim, Du Sung Jung
  • Publication number: 20140042604
    Abstract: Disclosed herein is a three-dimensional (3D) semiconductor package. The 3D semiconductor package includes a printed circuit board, a main interposer that is formed on the printed circuit board, a semiconductor device that is formed on the main interposer, and a support interposer that is disposed on the same plane as a plane of the semiconductor device, or disposed between the main interposer and the semiconductor device. Here, each of the main interposer, the semiconductor device, and the support interposer may include a through-via formed based on a thickness direction of the printed circuit board.
    Type: Application
    Filed: November 9, 2012
    Publication date: February 13, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyung Jin Jeon, Jong Yun Lee, Kyoung Moo Harr