Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

Abstract: An example electronic device includes a housing; a touchscreen display; a microphone; at least one speaker; a button disposed on a portion of the housing or set to be displayed on the touchscreen display; a wireless communication circuit; a processor; and a memory. When a user interface is not displayed on the touchscreen display, the electronic device enables a user to receive a user input through the button, receives user speech through the microphone, and then provides data on the user speech to an external server. An instruction for performing a task is received from the server. When the user interface is displayed on the touchscreen display, the electronic device enables the user to receive the user input through the button, receives user speech through the microphone, and then provides data on the user speech to the external server.

Abstract: A substrate processing apparatus includes a photoresist coater applying a photoresist film on a substrate, a humidifier increasing an amount of moisture in an ambient to which the photoresist film on the substrate is exposed, and an exposer irradiating the photoresist film exposed to the ambient having the increased amount of moisture with light. The humidifier is disposed between the photoresist coater and the exposer.

Abstract: A substrate processing apparatus includes: a conveyor belt configured to have an outer surface on which a bottom surface of a substrate is seated; and a polishing head unit configured to face an upper surface of the substrate, wherein the polishing head unit includes: a polishing head connected to a driver; a polishing pad configured to face the polishing head; a polishing pad fixing ring disposed between the polishing head and the polishing pad; and a temperature sensor configured to overlap the polishing pad fixing ring and to be spaced apart from the polishing pad fixing ring.

Abstract: Sense amplifier drive circuits drive a sense amplifier in a semiconductor (integrated circuit) memory device. A sense amplifier drive signal generator is configured to generate a sense amplifier drive signal responsive to at least one predecoded column address received at an input thereof. The sense amplifier drive signal generator may receive predecoded column addresses from a column predecoder. A delay circuit coupled to the sense amplifier drive signal generator may delay the sense amplifier drive signal by a selected time and output a delayed sense amplifier drive signal for driving the sense amplifier. The selected time may be based on a time from activation of a bit line selection signal of the semiconductor (integrated circuit) memory device to application of selected data to the sense amplifier. Corresponding methods are also provided.

Abstract: Integrated circuit memory devices include a first memory block. The first memory block includes first and second memory array banks and a first peripheral circuit. The first peripheral circuit is disposed between the first and second memory array banks such that a length of a first data path from the first memory array bank to the first peripheral circuit is about equal to a length of a second data path from the second memory array bank to the first peripheral circuit.

Abstract: Integrated circuit devices include a control circuit that selectively drive a power supply terminal of a memory cell array and a sense amplifier of the integrated circuit device with a first power supply voltage and/or a second power supply voltage responsive to a control signal. The second power supply voltage is delivered to the integrated circuit device separate from the first power supply voltage. The integrated circuit device may further include an internal voltage generator circuit powered by an external power supply separate from the second power supply voltage and the first power supply voltage may be an internal voltage generated by the internal voltage generator circuit. The integrated circuit device may also include a data output circuit that is powered by the second power supply voltage. Corresponding methods are also provided.

Abstract: Methods of terminating an external transmission line in a memory device having an on-die termination circuit include electrically coupling the termination circuit to the transmission line in response to a control signal which indicates that the memory device is in an active mode or a write mode. The termination circuit has an impedance value that is mismatched with an impedance value of the transmission line. The termination circuit can include an input/output pad, a resistor, and a transistor connected in series to a reference voltage. Also, the termination circuit may be electrically coupled to the transmission line by activating the transistor in the termination circuit to connect the transmission line to the reference voltage in response to the control signal. Related devices are also disclosed.

Abstract: A semiconductor memory device includes a data controller for generating a data signal in response to data generated at an internal circuit of the semiconductor memory device when a latency signal, which sets the latency of the semiconductor memory device, is activated. The device includes an output driver for generating a data strobe signal in response to the data signal, a preamble controller for outputting a preamble control signal in response to a read command input to the semiconductor memory device, and a preamble unit for preambling the data strobe signal by changing an output signal of the output driver from a logic high level to a logic low level, when the preamble control signal is activated. Data output from the semiconductor memory device has a satisfactory preamble section.

Abstract: Sense amplifier drive circuits drive a sense amplifier in a semiconductor (integrated circuit) memory device. A sense amplifier drive signal generator is configured to generate a sense amplifier drive signal responsive to at least one predecoded column address received at an input thereof. The sense amplifier drive signal generator may receive predecoded column addresses from a column predecoder. A delay circuit coupled to the sense amplifier drive signal generator may delay the sense amplifier drive signal by a selected time and output a delayed sense amplifier drive signal for driving the sense amplifier. The selected time may be based on a time from activation of a bit line selection signal of the semiconductor (integrated circuit) memory device to application of selected data to the sense amplifier. Corresponding methods are also provided.

Abstract: A data buffer circuit includes first and second driver circuits coupled to the data latch circuit and operative to respectively pull up and pull down their outputs towards respective first and second voltages responsive to first and second data signals. An output circuit includes first and second transistors connected at an output node and operative to respectively pull up and pull down the output node toward respective ones of the first and second voltages responsive to respective ones of the outputs of the first and second driver circuits. A transition compensation circuit is operative to control relative rates at the output node of the output circuit transitions toward the first and second voltages responsive to a transition rate control signal.

Abstract: Integrated circuit memory devices include a first memory block. The first memory block includes first and second memory array banks and a first peripheral circuit. The first peripheral circuit is disposed between the first and second memory array banks such that a length of a first data path from the first memory array bank to the first peripheral circuit is about equal to a length of a second data path from the second memory array bank to the first peripheral circuit.

Abstract: Integrated circuit devices include a control circuit that selectively drive a power supply terminal of a memory cell array and a sense amplifier of the integrated circuit device with a first power supply voltage and/or a second power supply voltage responsive to a control signal. The second power supply voltage is delivered to the integrated circuit device separate from the first power supply voltage. The integrated circuit device may further include an internal voltage generator circuit powered by an external power supply separate from the second power supply voltage and the first power supply voltage may be an internal voltage generated by the internal voltage generator circuit. The integrated circuit device may also include a data output circuit that is powered by the second power supply voltage. Corresponding methods are also provided.

Abstract: A semiconductor memory device includes a data controller for generating a data signal in response to data generated at an internal circuit of the semiconductor memory device when a latency signal, which sets the latency of the semiconductor memory device, is activated. The device includes an output driver for generating a data strobe signal in response to the data signal, a preamble controller for outputting a preamble control signal in response to a read command input to the semiconductor memory device, and a preamble unit for preambling the data strobe signal by changing an output signal of the output driver from a logic high level to a logic low level, when the preamble control signal is activated. Data output from the semiconductor memory device has a satisfactory preamble section.

Abstract: A data buffer circuit includes first and second driver circuits coupled to the data latch circuit and operative to respectively pull up and pull down their outputs towards respective first and second voltages responsive to first and second data signals. An output circuit includes first and second transistors connected at an output node and operative to respectively pull up and pull down the output node toward respective ones of the first and second voltages responsive to respective ones of the outputs of the first and second driver circuits. A transition compensation circuit is operative to control relative rates at the output node of the output circuit transitions toward the first and second voltages responsive to a transition rate control signal.

Abstract: A memory device includes a plurality of memory banks, a plurality of data line pairs coupled to the memory banks, and an input/output (IO) sense amplifier shared by at least two neighboring memory banks. The IO sense amplifier includes a plurality of current sense amplifiers and a latch sense amplifier. Each current sense amplifier couples to and senses a corresponding data line pair. The latch sense amplifier selectively senses signals from the plurality of current sense amplifiers and generates an output signal at a suitable voltage for peripheral circuitry. Circuit area required for sense amplifiers is reduced because at least two memory banks share a latch sense amplifier, instead of having one latch sense amplifier for each memory bank.

Abstract: A semiconductor memory device such as a DRAM maintains uniform sensing efficiency of a data line sense amplifier The memory device includes multiple memory blocks, and each memory block containing bit line sense amplifies, load transistors, and switching transistors. The load transistors generate a current on the data lines when the respective memory block is selected for a read operation. The switching transistors connect the respective bit line sense amplifiers to data line pairs. The sizes of the load and switching transistors can adjust for different distances along data lines between the respective bit line sense amplifiers and data line sense amplifiers. Accordingly, the data line sense amplifiers have uniform sensing efficiency regardless of the transmission distance.

Abstract: Multi-bank memory devices include a plurality of memory banks and a plurality of data buses that are connected to the memory banks in a manner that enables the efficient use of a reduced number of shared sense amplifiers and driver circuits during reading and writing operations. The memory device has a plurality of memory banks therein with each memory bank comprising a plurality of memory blocks. A plurality of data buses are also provided and each of these data buses is preferably coupled to at least two of the memory banks so that shared reading and writing operations can be performed in an efficient manner using bank selection switches.

Abstract: Data masking is performed for an integrated circuit memory device, by generating a pulse in response to a data masking signal that is received on one of a plurality of data masking pins, equalizing a plurality of groups of input/output line pairs during the pulse and precharging the plurality of groups of input/output line pairs during the pulse. The group of input/output line pairs that correspond to the data masking signal then is precharged after the pulse in response to the data masking signal that is received on the one of the plurality of data masking pins. The input and output line drivers also preferably are deactivated during the pulse and the input and output line drivers, except for the group of input and output line drivers that correspond to the one of the plurality of data masking pins, preferably are activated after the pulse.

Abstract: A data output buffer control circuit for a semiconductor memory device assures a column address setup time and a valid data setup time in EDO mode by eliminating short glitches in the data output buffer. The circuit assures the column address setup time by disabling the data output buffer for a predetermined period of time after an address transition, regardless of the state of a column address strobe signal. The circuit assures the setup time for valid data by sensing when the address is set up relative to when the column address strobe signal is activated, and then enabling the data output buffer so as to maintain invalid data in the data output buffer long enough to prevent a short glitch in the data output buffer if the column address is set up before the column address strobe signal is activated.