Abstract: A data output buffer control circuit for a semiconductor memory device assures a column address setup time and a valid data setup time in EDO mode by eliminating short glitches in the data output buffer. The circuit assures the column address setup time by disabling the data output buffer for a predetermined period of time after an address transition, regardless of the state of a column address strobe signal. The circuit assures the setup time for valid data by sensing when the address is set up relative to when the column address strobe signal is activated, and then enabling the data output buffer so as to maintain invalid data in the data output buffer long enough to prevent a short glitch in the data output buffer if the column address is set up before the column address strobe signal is activated.

Abstract: A semiconductor device can be configured for compatibility with different system level interfaces, e.g., LVTTL or SSTL, after assembly, thereby eliminating the need for bonding options and reducing the cost of manufacturing the device. The device includes an interface dependent circuit that operates with a selected interface in response to one or more interface enable signals. Several alternative embodiments include interface control circuits and mode register circuits for generating the interface enable signals responsive to a row address and control signals such as RAS, CAS, WE, and CS. Some embodiments also include a switching network that allows an input buffer to use an internally generated reference voltage for one interface and an externally applied reference voltage for a second interface.

Abstract: An input buffer that can operate with Low Voltage Transistor-Transistor Logic (LVTTL) and with Stub Series Terminated transceiver Logic (SSTL) includes a differential amplifier that differentially amplifies a reference voltage and an external input signal. A switching system is coupled to the differential amplifier, to supply an external power supply voltage to the differential amplifier under SSTL operating conditions and to supply an internal power supply voltage to the differential amplifier under LVTTL operating conditions. An internal power supply voltage generator is responsive to the external power supply voltage, to generate the internal power supply voltage therefrom. The internal power supply voltage generator supplies the internal power supply voltage to the switching system. The switching system preferably includes a first switch that supplies the external power supply voltage to the differential amplifier in response to an SSTL control signal.

Abstract: A memory device having normal and extended data out (EDO). modes includes an array of memory cells arranged in plurality of rows and columns, first and second data latches which store data, a column address input which receives a column address signal, and a column address strobe input which receives a column address strobe signal. First latch control means, responsive to said column address input and to the column address strobe input, electrically couples one memory cell in the array of memory cells and the first data latch when a column address signal is asserted at the column address input and electrically decouples the one memory cell and the first data latch when a column address strobe signal is asserted at the column address strobe input, thereby latching data present in the one memory cell prior to assertion of the column address strobe signal in the first data latch.

Abstract: A bit line sense amplifier in a semiconductor memory device having a sense amplifier for sensing and amplifying a logic slate of data stored in a selected memory cell in response to a row address and for outputting sense-amplified data to a bit line pair, and transmission means for transmitting output data of the bit line pair to the corresponding input/output line pair thereto. The bit line sense amplifier includes a secondary power supply voltage generating circuit for supplying a secondary power supply voltage and a secondary ground potential in response to a block selection signal for selecting a memory block including the selected memory cell, and a secondary sense amplifier being supplied with the secondary power supply voltage and secondary ground potential, and for converting data indicative of a potential difference of the bit line pair and input/output line pair to a level of the secondary power supply voltage and ground potential in response to the column selection signal.

Abstract: A data output buffer of a semiconductor integrated circuit is operable in response to data input to data lines and comprises a first pull-down control circuit which generates a first pull-down signal in response to the data input to the data lines. A second pull-down control circuit generates a second pull-down signal in response to the data input to the data lines, the second pull-down signal being generated at a predetermined time after the first pull-down signal is generated and causing the first pull down signal to be deactivated. A first pull-down transistor shares an output node with a pull-up transistor and is responsive to the first pull-down signal to pull-down a predetermined amount of voltage at the output node. A second pull-down transistor is responsive to the second pull down signal for pulling down a residual amount of voltage at the output node.

Abstract: Disclosed is a refresh address test circuit of a semiconductor memory device having a self-refresh function using a plurality of internal refresh address signals, comprising a plurality of the address test paths, each including a first sub-path which receives an initial logic level of one bit of an initial refresh address and a second sub-path of which receives successive corresponding bits of said refresh address, a plurality of comparators, each connected to the first sub-path and the second sub-path, a test output circuit receives the output signals generated from the plurality of comparators to determine whether a complete cycle of refresh addresses have been generated.