Patents by Inventor Larry Wang

Larry Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040065897
    Abstract: The safe-operating area (SOA) in a heterojunction bipolar transistor (HBT) is improved by providing a collector region in the transistor having a graded (uniformly or stepped) doping between the base region and the underlying subcollector region with the collector doping being lower near the base and higher near the subcollector and with the collector doping being less than the doping of the subcollector. The non-uniformly doped collector reduces Kirk effect induced breakdown when collector current increases.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 8, 2004
    Applicant: EiC Corporation
    Inventors: Chien Ping Lee, Hin Fai Chau, Nanlei Larry Wang, Clarence John Dunnrowicz, Yan Chen, Barry Jia-Fu Lin
  • Patent number: 6700076
    Abstract: An electronic module includes an interconnect module having a plurality of metal layers separated by a plurality of dielectric layers in a stacked structure with electronic components mounted on one surface of the module. The electronic components are selectively interconnected by drilling via holes completely through all dielectric layers with a conductive material such as solder in each via contacting metal layers to be interconnected and each metal layer which is not connected by a via having a metal pattern devoid of metal at the via location. For via connecting non-ground layers, there will be a patch of solder mask on the backside ground layer to electrically prevent this via from inadvertently connecting to ground.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: March 2, 2004
    Assignee: EIC Corporation
    Inventors: Xiao-Peng Sun, Nanlei Larry Wang
  • Patent number: 6599810
    Abstract: An insulated trench isolation structure is formed by ion implanting impurities proximate to the trench edges for enhancing the oxidation rate and, hence, increasing the thickness of the oxide at the trench edges. Embodiments include ion implanting impurities prior to growing an oxide liner. The resulting thick oxide on the trench edges avoids overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.
    Type: Grant
    Filed: November 5, 1998
    Date of Patent: July 29, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nick Kepler, Olov Karlsson, Larry Wang, Basab Bandyopadhyay, Effiong Ibok, Christopher F. Lyons
  • Patent number: 6580881
    Abstract: Waste toner is detected in a container of an image forming apparatus. An auger is provided within the container. A switch is provided which is operable depending upon a torque associated with operation of the auger. A frequency of activation of the switch is detected. A “not full”, “near full” and “full” condition of the waste toner in the container is determined depending upon the frequency of activation of the switch.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: June 17, 2003
    Assignee: Lexmark International, Inc.
    Inventors: Matthew Christopher Coriale, Jonathan Carey Frey, Harald Portig, John Parker Richey, Wen-hsiung Adam Tseng, Liqun Larry Wang
  • Patent number: 6556082
    Abstract: A temperature compensating circuit for use with a current mirror circuit for maintaining a reference current value during temperature variations includes a compensating transistor connected in parallel with a reference current transistor and bias circuitry for biasing the compensating transistor whereby current flows from the reference node to ground through the compensating transistor to remove excess current from the reference transistor when temperature increases. A diode can be included in the bias circuitry for limiting bias current flow when the reference voltage drops below the voltage drop of the diode. An on/off switch circuit can be provided in parallel with the reference current transistor to further reduce reference current in specific applications.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: April 29, 2003
    Assignee: EiC Corporation
    Inventors: Nanlei Larry Wang, Sarah Xu, Shuo-Yuan Hsiao
  • Patent number: 6553195
    Abstract: An end seal for use in an electrophotographic image forming apparatus uses an array of ridges (or grooves) to urge toner inwardly so as to help prevent toner escape. The end seal works in conjunction with a cleaning blade. The end seal includes a blade pocket for mating with the end portions of the cleaning blade and a middle portion having an array of ridges thereon. The ridges are angled inward to urge any toner trapped therebetween inward away from the end seals, where the toner can be directed to a waste reservoir in a normal fashion. This “snowplowing” action of the ridges helps prevent outward migration of toner, thereby minimizing toner escape. The end seal may be composed of two or more layers of differing materials. There may be an end seal at each end of the cleaner blade.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: April 22, 2003
    Inventors: Kurt Matthew Korfhage, Michael David Maul, Alexander Douglas Meade, Tom E Stickler, Liqun Larry Wang
  • Publication number: 20030071688
    Abstract: A temperature compensating circuit for use with a current mirror circuit for maintaining a reference current value during temperature variations includes a compensating transistor connected in parallel with a reference current transistor and bias circuitry for biasing the compensating transistor whereby current flows from the reference node to ground through the compensating transistor to remove excess current from the reference transistor when temperature increases. A diode can be included in the bias circuitry for limiting bias current flow when the reference voltage drops below the voltage drop of the diode. An on/off switch circuit can be provided in parallel with the reference current transistor to further reduce reference current in specific applications.
    Type: Application
    Filed: October 12, 2001
    Publication date: April 17, 2003
    Applicant: EiC Corporation
    Inventors: Nanlei Larry Wang, Sarah Xu, Shuo-Yuan Hsiao
  • Publication number: 20030068167
    Abstract: Waste toner is detected in a container of an image forming apparatus. An auger is provided within the container. A switch is provided which is operable depending upon a torque associated with operation of the auger. A frequency of activation of the switch is detected. A “not full”, “near full” and “full” condition of the waste toner in the container is determined depending upon the frequency of activation of the switch.
    Type: Application
    Filed: October 4, 2001
    Publication date: April 10, 2003
    Inventors: Matthew Christopher Coriale, Jonathan Carey Frey, Harald Portig, John Parker Richey, Wen-Hsiung Adam Tseng, Liqun Larry Wang
  • Patent number: 6546225
    Abstract: A waste toner container and auger therefor. Auger flights have a continuously decreasing flight pitch from the front of the auger to the back of the auger. The auger includes a flightless portion near the back wall of the container.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: April 8, 2003
    Assignee: Lexmark International, Inc.
    Inventor: Liqun Larry Wang
  • Publication number: 20030059227
    Abstract: An end seal for use in an electrophotographic image forming apparatus uses an array of ridges (or grooves) to urge toner inwardly so as to help prevent toner escape. The end seal works in conjunction with a cleaning blade. The end seal includes a blade pocket for mating with the end portions of the cleaning blade and a middle portion having an array of ridges thereon. The ridges are angled inward to urge any toner trapped therebetween inward away from the end seals, where the toner can be directed to a waste reservoir in a normal fashion. This “snowplowing” action of the ridges helps prevent outward migration of toner, thereby minimizing toner escape. The end seal may be composed of two or more layers of differing materials. There may be an end seal at each end of the cleaner blade.
    Type: Application
    Filed: September 27, 2001
    Publication date: March 27, 2003
    Inventors: Kurt Matthew Korfhage, Michael David Maul, Alexander Douglas Meade, Tom E. Stickler, Liqun Larry Wang
  • Patent number: 6522201
    Abstract: Efficiency of an RF/microwave power amplifier is increased at a back-off power level by increasing the load resistance of the amplifier at the reduced output power level as compared to load impedance at a higher power level including full operating power. The different load impedances can be realized with two amplification units in parallel each having different load impedances. Alternatively, a single amplification path can be provided with an output impedance matching network which is selectively bypassed for increased impedance load during back-off power operation. In another embodiment, the output impedance matching network can include a shunt inductance which is selectively switched into the network to increase impedance for back-off power operation.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: February 18, 2003
    Assignee: EiC Corporation
    Inventors: Shuo-Yuan Hsiao, Wei-Shu Zhou, Nanlei Y Larry Wang
  • Patent number: 6521972
    Abstract: An RF microwave power transistor has an input/output feed structure which functions as a low impedance microstrip line by providing a ground plane in close proximity to the feed structure on one surface of a semiconductor body. A second ground plane can be provided on an opposing surface of the semiconductor body with vias interconnecting the first and second ground planes. In addition to reducing feed impedance, a larger total transistor size can be provided before “odd mode oscillation” occurs.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: February 18, 2003
    Assignee: EiC Corporation
    Inventors: Wei-Shu Zhou, Shuo-Yuan Hsiao, Nanlei Larry Wang
  • Patent number: 6463254
    Abstract: A toner cleaning apparatus for a printing device includes a toner separator operating against a component of the printing device, to dislodge toner particles therefrom. A toner receptacle is provided for collecting the dislodged toner particles, and an auger positively conveys the dislodged toner particles into the toner receptacle. A vibration plate is provided for receiving the toner particles dislodged by the toner separator, and for directing the dislodged toner particles to the auger. The vibration plate includes lengths thereof extending into the auger and deflected by the auger to induce vibrations along the plate and distribute-and convey toner particles disposed thereon.
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: October 8, 2002
    Assignee: Lexmark International, Inc.
    Inventors: Michael David Maul, Alexander Douglas Meade, Liqun Larry Wang
  • Publication number: 20020114651
    Abstract: A waste toner container and auger therefor. Auger flights have a continuously decreasing flight pitch from the front of the auger to the back of the auger. The auger includes a flightless portion near the back wall of the container.
    Type: Application
    Filed: February 21, 2001
    Publication date: August 22, 2002
    Inventor: Liqun Larry Wang
  • Publication number: 20020105083
    Abstract: An electronic module includes an interconnect module having a plurality of metal layers separated by a plurality of dielectric layers in a stacked structure with electronic components mounted on one surface of the module. The electronic components are selectively interconnected by drilling via holes completely through all dielectric layers with a conductive material such as solder in each via contacting metal layers to be interconnected and each metal layer which is not connected by a via having a metal pattern devoid of metal at the via location. For via connecting non-ground layers, there will be a patch of solder mask on the backside ground layer to electrically prevent this via from inadvertently connecting to ground.
    Type: Application
    Filed: February 1, 2002
    Publication date: August 8, 2002
    Applicant: EiC Corporation
    Inventors: Xiao-Peng Sun, Nanlei Larry Wang
  • Publication number: 20020097094
    Abstract: A hybrid microwave and millimeter wave integrated circuit (MMIC) RF power amplifier includes an integrated circuit in which an amplifier circuit is fabricated and an output impedance matching network comprising metal-insulator-metal (MIM) capacitors mounted on the integrated circuit chip with bonding wire inductors connecting the amplifier circuit with the capacitor elements. The resulting structure has a smaller form factor as compared to conventional power amplifiers employing planar transmission lines and surface mount technology capacitors.
    Type: Application
    Filed: January 19, 2001
    Publication date: July 25, 2002
    Applicant: EiC Corporation
    Inventors: Nanlei Larry Wang, Shuo-Yuan Hsiao, Xiao-Peng Sun
  • Patent number: 6424223
    Abstract: A hybrid microwave and millimeter wave integrated circuit (MMIC) RF power amplifier includes an integrated circuit in which an amplifier circuit is fabricated and an output impedance matching network comprising metal-insulator-metal (MIM) capacitors mounted on the integrated circuit chip with bonding wire inductors connecting the amplifier circuit with the capacitor elements. The resulting structure has a smaller form factor as compared to conventional power amplifiers employing planar transmission lines and surface mount technology capacitors.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: July 23, 2002
    Assignee: EiC Corporation
    Inventors: Nanlei Larry Wang, Shuo-Yuan Hsiao, Xiao-Peng Sun
  • Patent number: 6380047
    Abstract: An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate with improved planarity using a simplified reverse source/drain planarization mask. Embodiments include forming large trenches and refilling them with an insulating material which also covers the substrate surface, masking the areas above the large trenches, etching to remove substantially all of the insulating material on the substrate surface and polishing to planarize the insulating material above the large trenches. Small trenches and peripheral trenches surrounding the large trenches are then formed, refilled with insulating material, and planarized. Since the large trenches are formed prior to and separately from the small trenches, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: April 30, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Basab Bandyopadhyay, Nick Kepler, Olov Karlsson, Larry Wang, Effiong Ibok, Christopher F. Lyons
  • Patent number: 6380040
    Abstract: High integrity cobalt silicide contacts are formed with shallow source/drain junctions. Embodiments include depositing a layer of cobalt on a substrate above intended source/drain regions, followed by silicidation and diffusing impurities from a doped film during or after silicidation in an environment which discourages out-diffusion of the impurities to the environment. The resulting source/drain junctions are self-aligned to the cobalt silicide/silicon substrate interface, thereby preventing junction leakage while advantageously enabling forming the cobalt silicide contacts at optimum thickness to avoid parasitic series resistances. The formation of self-aligned source/drain junctions to the cobalt silicide/silicon substrate interface facilitates reliable device scaling, while the avoidance of unwanted diffusion of impurities to the environment assures adequate doping of the source/drain regions.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: April 30, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nick Kepler, Karsten Wieczorek, Larry Wang, Paul R. Besser
  • Patent number: 6326849
    Abstract: In an RF amplifier circuit having a plurality of transistor stages with each transistor having an input terminal for receiving an RF signal, a bias circuit is provided for applying a DC bias to the input terminal of a transistor. An isolation circuit connects a DC power supply to a bias circuit whereby DC voltage from the power terminal is applied to the bias circuit and RF signal from the transistor input terminal is attenuated. The isolation circuit includes a reactive serial path which allows the flow of DC current and presents an impedance to RF current flow and a reactive shunt path to ground which can comprise a capacitor or a serial inductor/capacitor circuit. The reactive serial path can comprise an inductor or an inductor/capacitor parallel circuit.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: December 4, 2001
    Assignee: EiC Corporation
    Inventors: Nanlei Larry Wang, Shuo-Yuan Hsiao, Wei-Shu Zhou, Shihui Xu