Abstract: A method for ensuring data integrity in a computer system having a primary logical device and one or more alternate logical devices. These logical devices have substantially identical data stored in them and have the capability of responding to requests. The system duplicates device access to the alternate logical devices. The logical devices are identified to the computer system as the devices on which duplicating or mirroring operations are to be performed. A read operation or a write operation is performed on the primary logical device. In the case of a write operation, it is also performed simultaneously on the alternate logical devices. The system waits for a response from the primary logical device. If the response indicates that the primary logical device has failed, the alternate logical devices are relied on to complete the operation.

Abstract: A depression is formed by mesa etching or the like in the surface of an insulative substrate. A first semiconductive layer structure such as a PNP layer structure is formed on the surface including the depression. An electrically insulative isolation layer is formed on the first layer structure, and then a second layer structure such as an NPN layer structure is formed on the isolation layer. The area over the depression is then masked, and the second layer structure and isolation layer are etched away from the first layer structure over areas of the surface external of the depression. Where the thicknesses of the first and second layer structures are equal, and the depth of the depression is equal to the combined thicknesses of the first layer structure and the isolation layer, the second layer structure laterally external of the depression will be coplanar with the first layer structure over the depression.

Abstract: A digital correction circuit for use in signal converters is disclosed. The invention includes a subtractor (32) for subtracting a digital correction signal from an input signal, a digital filter (34) for filtering the output of the subtractor to provide a digital output signal and memory (39) for providing said correction signal. In a specific embodiment of the invention, an improved analog-to-digital converter is disclosed including an improved digital-to-analog converter with digital correction circuitry.

Abstract: A high speed digital programmable frequency divider (100) capable of frequency division by even and odd integers is disclosed herein. The frequency divider (100) of the present invention includes a waveform generator (200) for providing a periodic input waveform of a first period and the inverse thereof. The present invention further includes a clocked ring oscillator circuit (400) for providing first and second closed signal paths, in response to the input waveform, disposed to invert signals passing therethrough. The first and second signal paths have a common output node (499) and first and second propagation delays substantially equal to first and second integral multiples of the first period, respectively. In addition, the frequency divider (100) includes a programmable switch network (500) for opening the first and second signal paths to provide a periodic output waveform at the output node (499).

Abstract: An analog-to-digital converter 10 employs a series of comparators 12, 14, 16 and 18. Each comparator includes at least one inverter consisting of a CMOS transistor pair including a P-channel transistor 22 and N-channel transistor 24. The threshold levels of the transistors 22, 24 are modified using focused ion beam implantation techniques to provide the comparators with monotonically increasing transistion levels.

Abstract: A first data processing system sends a message to a second data processing system via a modem. A processor of the first data processing system executes the instructions of an encoding algorithm stored in a memory of the first data processing system thereby encoding the characters of the message as the message is sent from the first system to the second system. The processor, in conjunction with the encoding algorithm, encodes the characters of the message by locating unacceptable characters among the acceptable characters in the message, the unacceptable characters possessing more than one meaning and triggering the execution of a function other than the intended function. The acceptable characters do not possess any alternative meanings. A bias code is selected for the acceptable characters and a further bias code is selected for the unacceptable characters. The unacceptable characters are converted into modified acceptable characters.

Abstract: A translator writing system develops a translator program capable of transforming a user's source code into object code. The language of the source code is summarized in a unique form, namely, a Backus-Nauer Form (BNF). This BNF form of the source code is utilized by the translator writing system to transform the source code into object code. The BNF form takes into account the attribute specifications associated with the language of the source code and the interaction of the attribute specifications in the grammar of the language of the source code. The translator writing system includes a valid testcase generator for testing the developed translator program utilizing every possible correct program statement in the language of the user's source code. The translator writing system further includes an incorrect, invalid testcase generator for testing the developed translator program utilizing every possible incorrect, invalid program statement in the language of the user's source code.

Abstract: A high resolution pipelined digital-to-analog converter is disclosed having at least one switching circuit for conveying charge to at least one conversion capacitor upon receipt of a digital signal during the first half of a clock cycle. Additional switching circuits are provided for transferring the charge from the conversion capacitors to a feedback capacitor during the second half of the clock cycle. Also provided is a circuit for discharging an analog output from, and preventing the charging of, the feedback capacitor during the first half of a succeeding clock cycle. In a preferred embodiment, the pipelined digital-to-analog converter comprises a first plurality of electrical circuits having at least one feedback capacitor and a plurality of conversion capacitors adapted for accepting digital and analog inputs, wherein the ratio of the feedback capacitance to each of the conversion capacitances is substantially independent of the resolution of the converter.

Abstract: A compression and a decompression algorithm resides in a memory of a data processing system. The data processing system communicates to another data processing system via an input/output means and a telecommunications network. When a message, to be communicated to the other data processing system, is ready for transmission, the data processing system compresses the message data. A processor of the data processing system compresses the data using the compression algorithm stored in the memory of the data processing system.