Abstract: The present disclosure provides a memristive array. The array includes a number of memristive devices. A memristive device is switchable between states and is to store information. The memristive array also includes a parallel reset control device coupled to the number of memristive devices in parallel. The parallel reset control device regulates a resetting operation for the number of memristive devices by regulating current flow through target memristive devices.

Abstract: In one example in accordance with the present disclosure a device is described. The device includes a cross-bar array of memristive elements. Each memristive element has a conductance value. The device also includes a column of offset elements. An offset element is coupled to a row of memristive elements and has a conductance value. The device also includes a number of accumulation elements. An accumulation element is coupled to a column of memristive elements. The accumulation element collects an intermediate output from the column and subtracts from the intermediate output an output from the column of offset elements.

Abstract: In one example in accordance with the present disclosure a device is described. The device includes at least two memristive cells. Each memristive cell includes a memristive element to store one component of a complex weight value. The device also includes a real input multiplier coupled to the memristive element to multiply an output signal of the memristive element with a real component of an input signal. An imaginary input multiplier of the device is coupled to the memristive element to multiply the output signal of the memristive element with an imaginary component of the input signal.

Abstract: An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.

Abstract: A memristive array includes a number of bit cells, each bit cell including a memristive element and a selecting transistor serially coupled to the memristive element. The array also includes a waveform generation device coupled to the number of bit cells. The waveform generation device generates a shaped waveform to be applied to the number of bit cells to switch a state of the memristive element. The waveform generation device passes the shaped waveform to gates of the selecting transistors of the number of bit cells.

Abstract: A circuit for a neuron of a multi-stage compute process is disclosed. The circuit comprises a weighted charge packet (WCP) generator. The circuit may also include a voltage divider controlled by a programmable resistance component (e.g., a memristor). The WCP generator may also include a current mirror controlled via the voltage divider and arrival of an input spike signal to the neuron. WCPs may be created to represent the multiply function of a multiply accumulate processor. The WCPs may be supplied to a capacitor to accumulate and represent the accumulate function. The value of the WCP may be controlled by the length of the spike in signal times the current supplied through the current mirror. Spikes may be asynchronous. Memristive components may be electrically isolated from input spike signals so their programmed conductance is not affected. Positive and negative spikes and WCPs for accumulation may be supported.

Abstract: In one example in accordance with the present disclosure a control circuit is described. The control circuit includes a source following component to receive an input voltage and output a switching voltage. The circuit also includes an input leg of a current mirror coupled to the source following component. The input leg of the current mirror replicates the switching voltage to an output leg of the current mirror of a memristive bit cell. The circuit also includes a number of current control components. At least one of the current control components enforces a constant current through the source following component and other current control components maintain the input leg of the current mirror and the output leg of the current mirror at the same current.

Abstract: According to examples, an apparatus may include a ternary content addressable memory (TCAM) including a plurality of TCAM bit cells connected in a row along a match line. Each of the TCAM bit cells may store a bit of a TCAM word and the TCAM bit cells may drive a digital signal over the match line in response to a search word matching the TCAM word. The apparatus may include a resistive random-access memory (RRAM) comprising a row of RRAM bit cells connected to the TCAM via the match line. Each of the RRAM bit cells may store a bit of a RRAM word. The RRAM bit cells may output the RRAM word in response to the TCAM bit cells driving the digital signal over the match line.

Abstract: An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.

Abstract: Examples herein relate to hardware accelerators for calculating node values of neural networks. An example hardware accelerator may include a crossbar array programmed to calculate node values of a neural network and a current comparator to compare an output current from the crossbar array to a threshold current according to an update rule to generate new node values. The crossbar array has a plurality of row lines, a plurality of column lines, and a memory cell coupled between each unique combination of one row line and one column line, where the memory cells are programmed according to a weight matrix. The plurality of row lines are to receive an input vector of node values, and the plurality of column lines are to deliver an output current to be compared with the threshold current.

Abstract: In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.

Abstract: An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.

Abstract: Comparators may be associated with dictionary entries. In one aspect, a dictionary entry may store a dictionary word. A register may store an input word. A comparator associated with the dictionary entry may compare the dictionary word and the input word. The comparison may be a bit by bit comparison. The comparator may output a signal indicating if the dictionary word is less than the input word, equal to the input word, or greater than the input word. The output may indicate indeterminate when the comparison is not yet complete.

Abstract: In one example in accordance with the present disclosure a memristive array is described. The memristive array includes a number of bit cells, each bit cell including a memristive element and a selecting transistor serially coupled to the memristive element. The array also includes a waveform generation device coupled to the number of bit cells. The waveform generation device generates a shaped waveform to be applied to the number of bit cells to switch a state of the memristive element. The waveform generation device passes the shaped waveform to gates of the selecting transistors of the number of bit cells.

Abstract: In one example in accordance with the present disclosure a control circuit is described. The control circuit includes a source following component to receive an input voltage and output a switching voltage. The circuit also includes an input leg of a current mirror coupled to the source following component. The input leg of the current mirror replicates the switching voltage to an output leg of the current mirror of a memristive bit cell. The circuit also includes a number of current control components. At least one of the current control components enforces a constant current through the source following component and other current control components maintain the input leg of the current mirror and the output leg of the current mirror at the same current.

Abstract: In one example in accordance with the present disclosure a memristive array is described. The array includes a number of memristive devices. A memristive device is switchable between states and is to store information. The memristive array also includes a parallel reset control device coupled to the number of memristive devices in parallel. The parallel reset control device regulates a resetting operation for the number of memristive devices by regulating current flow through target memristive devices.

Abstract: In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.

Abstract: A method, computer program product and computer system to generate a spatial visualization of topics contained in messages data is provided. A processor retrieves message data associated with a user. A processor determines one or more topics represented by the message data. A processor generates a spatial visualization of one or more user interface elements, where the spatial visualization includes a size and a location for the one or more user interface elements. A processor displays one or more user interface elements corresponding to the one or more topics.

Abstract: A method, computer program product and computer system to generate a spatial visualization of topics contained in messages data is provided. A processor retrieves message data associated with a user. A processor determines one or more topics represented by the message data. A processor generates a spatial visualization of one or more user interface elements, where the spatial visualization includes a size and a location for the one or more user interface elements. A processor displays one or more user interface elements corresponding to the one or more topics.

Abstract: Examples disclosed herein relate to neuron circuits and methods for generating neuron circuit outputs. In some of the disclosed examples, a neuron circuit includes a memristor and first and second current mirrors. The first current mirror may source a first current through the memristor and the second current mirror may sink a second current through the memristor. The memristor may generate a voltage output as a function of the sourced first current and the sunk second current through the memristor.