Abstract: Examples disclosed herein relate to programming a first conductance of a first resistive memory device based on a first target value. The first conductance of the first resistive memory device is measured to determine a deviation of the first resistive memory device from the first target value. A second target value of a second resistive memory device is adjusted based on the deviation, and a second conductance of the second resistive memory device is programmed based on the adjusted second target value.

Abstract: Examples disclosed herein relate to programming a first conductance of a first resistive memory device based on a first target value. The first conductance of the first resistive memory device is measured to determine a deviation of the first resistive memory device from the first target value. A second target value of a second resistive memory device is adjusted based on the deviation, and a second conductance of the second resistive memory device is programmed based on the adjusted second target value.

Abstract: An example device may include multiply-accumulate circuitry and voltage-tracking modulator circuitry. The multiply-accumulate circuitry may be to increase and decrease an accumulation voltage held by an accumulator based on a number of input signals. The voltage-tracking modulator circuitry may be to generate an output signal based on the accumulation voltage, wherein the output signal is a continuous-time binary signal that tracks changes of the accumulation voltage by varying pulse widths of the output signal. The example device may be used as a neuron in a neural network.

Abstract: Comparators may be associated with dictionary entries. In one aspect, a dictionary entry may store a dictionary word. A register may store an input word. A comparator associated with the dictionary entry may compare the dictionary word and the input word. The comparison may be a bit by bit comparison. The comparator may output a signal indicating if the dictionary word is less than the input word, equal to the input word, or greater than the input word. The output may indicate indeterminate when the comparison is not yet complete.

Abstract: Examples herein relate to hardware accelerators for calculating node values of neural networks. An example hardware accelerator may include a crossbar array programmed to calculate node values of a neural network and a current comparator to compare an output current from the crossbar array to a threshold current according to an update rule to generate new node values. The crossbar array has a plurality of row lines, a plurality of column lines, and a memory cell coupled between each unique combination of one row line and one column line, where the memory cells are programmed according to a weight matrix. The plurality of row lines are to receive an input vector of node values, and the plurality of column lines are to deliver an output current to be compared with the threshold current.

Abstract: Examples include a resistive random access memory (RRAM) array to support a redundant column. Some examples include an RRAM cell at a cross point of a column line and a row line of the RRAM array. A first column line may be coupled to a first input of a first current-steering multiplexer and the first current-steering multiplexer may have an output coupled to a first current sense amplifier and a select input coupled to a first column select signal. A second column line may be coupled to a second input of the first current-steering multiplexer and coupled to a first input of a second current-steering multiplexer. The second current-steering multiplexer may have an output coupled to a second current sense amplifier and a select input coupled to a second column select signal. A third column line may be coupled to a second input of the second current-steering multiplexer.

Abstract: An example device may include multiply-accumulate circuitry and voltage-tracking modulator circuitry. The multiply-accumulate circuitry may be to increase and decrease an accumulation voltage held by an accumulator based on a number of input signals. The voltage-tracking modulator circuitry may be to generate an output signal based on the accumulation voltage, wherein the output signal is a continuous-time binary signal that tracks changes of the accumulation voltage by varying pulse widths of the output signal. The example device may be used as a neuron in a neural network.

Abstract: In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.

Abstract: An example ternary content addressable memory. A bit cell of the memory may include a first memristor that has a first terminal that is connected to a first data line and a second terminal that is selectively connected to a second data line via a first switching transistor. The bit cell may also include a second memristor that has a first terminal that is connected to a third data line and a second terminal that is selectively connected to a fourth data line via a second switching transistor. The bit cell may also include a first match-line transistor and a second match-line transistor that are connected in series between a first rail and a match line, with a gate of the first match-line transistor being connected to the second terminal of the first memristor, and a gate of the second match-line transistor being connected to the second terminal of the second memristor.

Abstract: An example device in accordance with an aspect of the present disclosure includes a plurality of bit-cells coupled as an array. A bit-cell includes a first switch element, a second switch element, and a memory element coupled at a node. The plurality of bit-cells are coupled as the array based on a first bit-cell's memory element being coupled to a second bit-cell's node.

Abstract: Examples disclosed herein relate to neuron circuits and methods for generating neuron circuit outputs. In some of the disclosed examples, a neuron circuit includes a memristor and first and second current mirrors. The first current mirror may source a first current through the memristor and the second current mirror may sink a second current through the memristor. The memristor may generate a voltage output as a function of the sourced first current and the sunk second current through the memristor.

Abstract: An example ternary content addressable memory. A bit cell of the memory may include a first memristor that has a first terminal that is connected to a first data line and a second terminal that is selectively connected to a second data line via a first switching transistor. The bit cell may also include a second memristor that has a first terminal that is connected to a third data line and a second terminal that is selectively connected to a fourth data line via a second switching transistor. The bit cell may also include a first match-line transistor and a second match-line transistor that are connected in series between a first rail and a match line, with a gate of the first match-line transistor being connected to the second terminal of the first memristor, and a gate of the second match-line transistor being connected to the second terminal of the second memristor.

Abstract: Examples include a resistive random access memory (RRAM) array to support a redundant column. Some examples include an RRAM cell at a cross point of a column line and a row line of the RRAM array. A first column line may be coupled to a first input of a first current-steering multiplexer and the first current-steering multiplexer may have an output coupled to a first current sense amplifier and a select input coupled to a first column select signal. A second column line may be coupled to a second input of the first current-steering multiplexer and coupled to a first input of a second current-steering multiplexer. The second current-steering multiplexer may have an output coupled to a second current sense amplifier and a select input coupled to a second column select signal. A third column line may be coupled to a second input of the second current-steering multiplexer.

Abstract: An example ternary content addressable memory. A bit cell of the memory may include first and second memristors, with a first terminal of the first memristor being connected to a first terminal of the second memristor via a node, a second terminal of the first memristor being switchably connected to a first data line, and a second terminal of the second memristor being switchably connected to a second data line. The bit cell may also include a match-line transistor that is connected between a first rail and a match line, with a gate of the match-line transistor being connected to the node.

Abstract: An example device in accordance with an aspect of the present disclosure includes a plurality of bit-cells coupled as an array. A bit-cell includes a first switch element, a second switch element, and a memory element coupled at a node. The plurality of bit-cells are coupled as the array based on a first bit-cell's memory element being coupled to a second bit-cell's node.

Abstract: An example content addressable memory. A bit cell of the memory may include a memristor and a switching transistor that are connected in series between a first data line and a second data line. The bit cell may also include a match-line transistor connected between a match line and a rail. A gate of the match-line transistor may be connected to a common node of the memristor and the switching transistor. The switching transistor may be sized such that its channel resistance when on is between a resistance associated with a low-resistance state of the memristor and a resistance associated with a high-resistance state of the memristor.

Abstract: In one aspect, techniques for providing a banked content addressable memory (CAM) with counters are provided. A dictionary word may be divided into a plurality of banks. A counter may be associated with each bank of the plurality of banks. The counter may count the number of times a segment of an input word aligned with the bank does not match. A scheduler may schedule comparison of banks with higher probability of not matching before banks with lower probability of not matching. The probability of not matching may be based on the counters.

Abstract: A method of operating a plurality of memristive cells coupled as a memristor array includes initializing a first select line, and, in parallel for a number of memristor cells in the first select line, determining whether a level of conductance of the memristor cells in the first select line are within a tolerance of a reference conductance, and, in response to a determination that the level of conductance is not within the tolerance of the reference conductance, adjusting the level of conductance for the memristor cells in the first select line.