Abstract: A (Z)-solanone has the steric formula of: with the name of (S,Z)-5-isopropyl-8-methyl-6,8-diene-2-one or (R,Z)-5-isopropyl-8-methyl-6,8-diene-2-one. A process for the preparation of the (Z)-type solanone and the use thereof in flavoring of cigarette shred are further disclosed. The process includes the following steps: (1) reacting isopentanal and methyl vinyl ketone, under the action of a catalyst and a co-catalyst, to give (S)-2-isopropyl-5-carbonylhexanal or (R)-2-isopropyl-5-carbonylhexanal; (2) reacting the (S)-2-isopropyl-5-carbonylhexanal or the (R)-2-isopropyl-5-carbonylhexanal obtained in step (1) with (iodomethyl)triphenylphosphonium iodide, to give (S,Z)-7-iodo-5-isopropyl-6-ene-2-one or (R,Z)-7-iodo-5-isopropyl-6-ene-2-one; and (3) reacting the (S,Z)-7-iodo-5-isopropyl-6-ene-2-one or the (R,Z)-7-iodo-5-isopropyl-6-ene-2-one obtained in step (2) with pinacol isopropenylborate in the presence of a catalyst to give the (Z)-solanone.

Abstract: Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.

Abstract: Disclosed is a polishing fluid for improving surfaces formed by fused deposition molding with ABS, consisting of 30%-40% by weight of polymethyl methacrylate and 60%-70% by weight of a mixture. This application further discloses a method of preparing the polishing fluid by mixing under heating. The polishing fluid provided herein can quickly form a film on surfaces of the workpiece to be processed and fill depressions of the surfaces of the workpiece while dissolving the protrusions on the surfaces to render the surfaces smooth and even.

Abstract: Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.

Abstract: Various semiconductor chips with solder capped probe test pads are disclosed. In accordance with one aspect of the present invention, a semiconductor chip is provided that includes a substrate, plural input/output (I/O) structures on the substrate and plural test pads on the substrate. Each of the test pads includes a first conductor pad and a first solder cap on the first conductor pad.

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.

Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

Abstract: Disclosed is a polishing fluid for improving surfaces formed by fused deposition molding with ABS, consisting of 30%-40% by weight of polymethyl methacrylate and 60%-70% by weight of a mixture. This application further discloses a method of preparing the polishing fluid by mixing under heating. The polishing fluid provided herein can quickly form a film on surfaces of the workpiece to be processed and fill depressions of the surfaces of the workpiece while dissolving the protrusions on the surfaces to render the surfaces smooth and even.

Abstract: Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.

Abstract: A method includes: receiving an emergency call request; initiating, according to the emergency call request, n emergency calls by simultaneously using n call modes, where n is an integer not less than 2; and when a connection is established for one of the n emergency calls, releasing other emergency calls for which no connection has been established. By means of the embodiments of the present invention, multiple emergency calls may be simultaneously made, and when any one of the multiple emergency calls is connected, other emergency calls are released, reducing an emergency call time.

Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.

Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.

Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.

Abstract: Various molded chip combinations and methods of manufacturing the same are disclosed. In one aspect, a molded chip combination is provided that includes a first semiconductor chip that has a first PHY region, a second semiconductor chip that has a second PHY region, an interconnect chip interconnecting the first PHY region to the second PHY region, and a molding joining together the first semiconductor chip, the second semiconductor chip and the interconnect chip.

Abstract: Various fan-out devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a redistribution layer structure that has plural conductor structures and plural glass interlevel dielectric layers. A glass encapsulant layer is positioned on the redistribution layer structure. A first semiconductor chip and a second semiconductor chip are positioned in the glass encapsulant layer and electrically connected by at least some of the conductor structures. A cap layer is on the encapsulant layer.

Abstract: Various molded chip combinations and methods of manufacturing the same are disclosed. In one aspect, a molded chip combination is provided that includes a first semiconductor chip that has a first PHY region, a second semiconductor chip that has a second PHY region, an interconnect chip interconnecting the first PHY region to the second PHY region, and a molding joining together the first semiconductor chip, the second semiconductor chip and the interconnect chip.

Abstract: A method is described and in one embodiment includes receiving at a top-of-rack (“TOR”) switch a notification concerning a virtual machine (“VM”), wherein the received notification identifies a host associated with the VM; determining whether the identified host is directly connected to the TOR switch; and if the identified host is not directly connected to the TOR switch, identifying an intermediate switch to which the identified host is directly connected; and determining whether the identified intermediate switch to which the identified host is directly attached is attached to the TOR switch.

Abstract: A method includes: receiving an emergency call request; initiating, according to the emergency call request, n emergency calls by simultaneously using n call modes, where n is an integer not less than 2; and when a connection is established for one of the n emergency calls, releasing other emergency calls for which no connection has been established. By means of the embodiments of the present invention, multiple emergency calls may be simultaneously made, and when any one of the multiple emergency calls is connected, other emergency calls are released, reducing an emergency call time.

Abstract: In an example, there is disclosed a network switch, including: an ingress interface; an egress interface; an endpoint repository network interface; and one or more logic elements including an endpoint admission control engine to: receive a packet on the ingress interface, the packet having an associated source Internet protocol (IP) address and virtual network identifier (VNI); query an endpoint repository via the endpoint repository network interface for the source IP address and VNI; determine that the source IP address and VNI are found in an endpoint repository database of the endpoint repository; and forward the packet to a destination IP address via the egress interface.