Abstract: A nickel-phosphorus alloy coating comprising a substrate having a surface; a nickel phosphorus alloy coating plated to the surface, the nickel phosphorus alloy consisting of phosphorus from 15.0 wt. percent to 20.9 wt. percent.

Abstract: A diffusion barrier coating on a nickel-based alloy substrate comprising the diffusion barrier being coupled to the substrate between the substrate and a composite material opposite the substrate, wherein the diffusion barrier comprises a nickel cobalt and chromium-aluminum-yttria powder material.

Abstract: A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.

Abstract: A diffusion barrier coating on a nickel-based alloy substrate comprising the diffusion barrier being coupled to the substrate between the substrate and a composite material opposite the substrate, wherein the diffusion barrier comprises a nickel phosphorus alloy material.

Abstract: A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells. The memory device further includes a control circuit configured to provide a control signal to control programming a target memory cell of the top memory cells. The gate terminal of the target memory cell are coupled to a selected word line of the word lines.

Abstract: Embodiments of this application provide a method and an apparatus for reducing co-channel interference, and a base station. The method includes: receiving, by a relay eNodeB ReNB, a propagation delay sent by a donor eNodeB DeNB, where the propagation delay is a delay of propagation between the DeNB and the ReNB; and adjusting, based on the propagation delay, timing parameters for sending uplink data and receiving downlink data by the ReNB, where the timing parameters are delays of the ReNB relative to the DeNB. The DeNB is used as a reference for the propagation delay between the DeNB and the ReNB, to delay timing of receiving the downlink data by the ReNB; and advance timing of sending the uplink data by the ReNB.

Abstract: When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.

Abstract: Provided herein are compounds of Formula (I): and pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof, wherein X, R1, R1a, R2a, R2b, R2c, R2d, are as defined herein, and Ring HET is a 6-membered monocyclic heteroaryl ring system of Formula: wherein L2, R13, G8, G10, G11, and G12 are as defined herein. Compounds of the present invention are useful for inhibiting CARM1 activity. Methods of using the compounds for treating CARM1-mediated disorders are also described.

Abstract: A solution is provided comprising a strong base, a corrosion inhibitor, wherein the strong base is an alkali metal hydroxide, wherein the corrosion inhibitor is at least one of an organic acid having a-COOH functional group or an alkali metal salt one of an organic acid having a-COOH functional groups.

Abstract: A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.

Abstract: Described herein are compounds of Formula (I), pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof. Compounds of the present invention are useful for inhibiting PRMT5 activity. Methods of using the compounds for treating PRMT5-mediated disorders are also described.

Abstract: A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The method includes the following steps. An alternating dielectric stack is formed on a substrate. An opening is formed penetrating the alternating dielectric stack in a thickness direction of the substrate. A blocking layer is formed on a sidewall of the opening. A trapping layer is formed in the opening, and the trapping layer is formed on the blocking layer. The trapping layer includes a lower portion and an upper portion disposed above the lower portion. A thickness of the upper portion in a horizontal direction is greater than a thickness of the lower portion in the horizontal direction. The thickness distribution of the trapping layer is modified for improving the electrical performance of the 3D memory device.

Abstract: A method of performing a programming operation to a three dimensional (3D) NAND memory device is disclosed. The method makes residual electrons trapped in storage regions of middle dummy memory cells of an unselected string of the 3D NAND memory device to be removed during the pre-charging phase, so as to reduce program disturb to an selected string which neighbors the unselected string.

Abstract: For grid-connected power converter control, a method estimates a d-axis grid voltage from a d-axis reference current modified with a d-axis current and a q-axis current modified with a filter inductive reactance. The method generates a q-axis current error from a direct current (DC) voltage input and a DC bus voltage. The method estimates an observer q-axis grid voltage from a q-axis voltage output. The q-axis grid voltage observer estimates the q-axis grid voltage in a direct/quadrature (dq) reference frame equivalent to an ABC to DQ reference frame transform. The method determines a d-axis voltage output as a function of a d-axis current error and a q-axis current modified with a filter inductive reactance. The method determines a q-axis voltage output as a sum of the q-axis current controller output and the observer q-axis grid voltage.

Abstract: When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.

Abstract: A semiconductor device is provided. The semiconductor device includes a channel structure that extends from a side of a substrate. The channel structure has sidewalls and a bottom region. The channel structure includes a bottom channel contact that is positioned at the bottom region, and a channel layer that is formed along the sidewalls and over the bottom channel contact. The channel structure further includes a high-k layer that is formed over the channel layer along the sidewalls of the channel structure and over the bottom channel contact.

Abstract: Embodiments of the present methods and systems are directed to a system and method for managing and editing accounting periods. Particularly, the embodiments are directed to a financial management system that allows for the recordation of financial transactions without first requiring the creation of a user-defined accounting period, and that further allows for the creation, modification, and closure of defined accounting periods.

Abstract: A method of forming a ceramic matrix composite component with cooling channels includes embedding a plurality of wires into a preform structure, densifying the preform structure with embedded wires, and removing the plurality of wires to create a plurality of corresponding channels within the densified structure.

Abstract: A method of performing a programming operation to a three dimensional (3D) NAND memory device is disclosed. The method makes residual electrons trapped in storage regions of middle dummy memory cells of the unselected string of the 3D NAND memory device to be removed during the pre-charging phase, so as to reduce program disturb to the selected string which neighbors the unselected string.

Abstract: A control method includes: establishing a connection by a first electronic device with a second electronic device through a connection component in an activated state; and in response to the established connection, switching, by the first electronic device, a target functional component called by the second electronic device from an inactivated state to an activated state to implement a target function corresponding to the target functional component of the first electronic device. A state of the first electronic device includes: a first state and a second state. When the first electronic device is in the first state, the connection component is in the activated state, the target functional component being in the inactivated state. A power consumption of the first electronic device in the first state is lower than a power consumption of the first electronic device in the second state.