Patents by Inventor Leland Chang
Leland Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11860702Abstract: Methods and systems for controlling current consumption by an electrical load of a first circuit board are described. In an example, a device of a first circuit board can measure a current being drawn by the electrical load of the first circuit board from a second circuit board. The device can generate a control signal based on a current difference between the measured current and a target current. The control signal can represent a load control parameter. The device can apply the control signal to the electrical load of the first circuit board to adjust a current consumption by the electrical load.Type: GrantFiled: December 15, 2020Date of Patent: January 2, 2024Assignee: International Business Machines CorporationInventors: Xin Zhang, Bruce Fleischer, Leland Chang
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Publication number: 20230099608Abstract: A system comprises an analog resistive processing unit (RPU) system, and one or more processors. The analog RPU system comprises an array of RPU cells. The one or more processors are configured to: configure the analog RPU system to implement a convolutional neural network comprising a convolutional layer comprising at least one kernel matrix; program the at least one array of RPU cells to store a transformed kernel matrix which is generated by applying a first transformation process to the kernel matrix using a first predefined transformation matrix; and utilize the analog RPU system to perform an analog convolution operation by performing analog matrix-vector multiplication operations using the transformed kernel matrix and input vectors of a transformed data matrix, to thereby generate a transformed convolution output matrix, wherein the transformed data matrix is generated by applying a second transformation process to a data matrix using a second predefined transformation matrix.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Swagath Venkataramani, Shubham Jain, Leland Chang
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Publication number: 20220187892Abstract: Methods and systems for controlling current consumption by an electrical load of a first circuit board are described. In an example, a device of a first circuit board can measure a current being drawn by the electrical load of the first circuit board from a second circuit board. The device can generate a control signal based on a current difference between the measured current and a target current. The control signal can represent a load control parameter. The device can apply the control signal to the electrical load of the first circuit board to adjust a current consumption by the electrical load.Type: ApplicationFiled: December 15, 2020Publication date: June 16, 2022Inventors: Xin Zhang, Bruce Fleischer, Leland Chang
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Patent number: 11295201Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.Type: GrantFiled: March 29, 2019Date of Patent: April 5, 2022Assignee: International Business Machines CorporationInventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
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Patent number: 11263518Abstract: A method is provided for forming a Deep Neural Network (DNN). The method includes quantizing deep learning data structures of the DNN into at least two modes using at least two scale factors, respectively. Each of the at least two modes corresponds to a respective one of the at least two scale factors. The method further includes identifying which of the at least two scale factors to use for a given one of the data structures based on a data distribution of the given one of the data structures. The quantizing step includes identifying when a tail of the given one of the data structures starts by (i) building a histogram of values in the given one of the data structures using successive bins; (ii) identifying a ratio of density between the successive bins; and (iii) checking whether the ratio of density is greater than a ratio of density threshold.Type: GrantFiled: October 4, 2019Date of Patent: March 1, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Swagath Venkataramani, Shubham Jain, Vijayalakshmi Srinivasan, Leland Chang
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Patent number: 11150712Abstract: Voltage on the output terminal of an inductor is obtained as a first input signal to a control block (CB); the inductor has an input terminal connected to a power switch and driver block at a switching node. A sense input voltage is obtained on an output terminal of a sensing circuit that is not directly connected to the switching node, as a second input signal to the CB. A voltage is generated on a first output terminal of the CB and is selected such that the CB can use its first and second input signals to infer the current through the inductor. A pulse width modulation (PWM) signal is generated on a second output terminal of the CB, based on the inferred current through the inductor; the second output signal from the CB is provided to a PWM input terminal of the power switch and driver block.Type: GrantFiled: April 30, 2019Date of Patent: October 19, 2021Assignee: International Business Machines CorporationInventors: Xin Zhang, Todd E. Takken, Andrew Ferencz, Leland Chang, Paul W. Coteus
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Patent number: 11114944Abstract: A multi-phase buck switching converter having grouped pairs of phases, each phase using two magnetically coupled air-core inductors. For each group, a first driver circuit controlling switching of a first power transistor switching circuit coupled to a first air-core inductor output for driving an output load at the first phase. A second driver circuit controlling switching of a second power transistor switching circuit coupled to a second air-core inductor output for driving said output load at the second phase. The first and second phases are spaced 180° apart. The coupled air-core inductors per group of such orientation, separation distance and mutual inductance polarity relative to each other such that magnetic coupling between the two or more inductors at each phase results in a net increase in effective inductance per unit volume. Each air-core inductor is a metal slab of defined length, height and thickness formed using back-end-of-line semiconductor manufacturing process.Type: GrantFiled: December 9, 2019Date of Patent: September 7, 2021Assignee: International Business Machines CorporationInventors: Xin Zhang, Todd E. Takken, Naigang Wang, Leland Chang
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Publication number: 20210103799Abstract: A method is provided for forming a Deep Neural Network (DNN). The method includes quantizing deep learning data structures of the DNN into at least two modes using at least two scale factors, respectively. Each of the at least two modes corresponds to a respective one of the at least two scale factors. The method further includes identifying which of the at least two scale factors to use for a given one of the data structures based on a data distribution of the given one of the data structures. The quantizing step includes identifying when a tail of the given one of the data structures starts by (i) building a histogram of values in the given one of the data structures using successive bins; (ii) identifying a ratio of density between the successive bins; and (iii) checking whether the ratio of density is greater than a ratio of density threshold.Type: ApplicationFiled: October 4, 2019Publication date: April 8, 2021Inventors: Swagath Venkataramani, Shubham Jain, Vijayalakshmi Srinivasan, Leland Chang
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Publication number: 20200348740Abstract: Voltage on the output terminal of an inductor is obtained as a first input signal to a control block (CB); the inductor has an input terminal connected to a power switch and driver block at a switching node. A sense input voltage is obtained on an output terminal of a sensing circuit that is not directly connected to the switching node, as a second input signal to the CB. A voltage is generated on a first output terminal of the CB and is selected such that the CB can use its first and second input signals to infer the current through the inductor. A pulse width modulation (PWM) signal is generated on a second output terminal of the CB, based on the inferred current through the inductor; the second output signal from the CB is provided to a PWM input terminal of the power switch and driver block.Type: ApplicationFiled: April 30, 2019Publication date: November 5, 2020Inventors: Xin Zhang, Todd E. Takken, Andrew Ferencz, Leland Chang, Paul W. Coteus
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Patent number: 10810487Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.Type: GrantFiled: August 22, 2016Date of Patent: October 20, 2020Assignee: International Business Machines CorporationInventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
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Patent number: 10628732Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.Type: GrantFiled: June 14, 2016Date of Patent: April 21, 2020Assignee: International Business Machines CorporationInventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
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Publication number: 20200112254Abstract: A multi-phase buck switching converter having grouped pairs of phases, each phase using two magnetically coupled air-core inductors. For each group, a first driver circuit controlling switching of a first power transistor switching circuit coupled to a first air-core inductor output for driving an output load at the first phase. A second driver circuit controlling switching of a second power transistor switching circuit coupled to a second air-core inductor output for driving said output load at the second phase. The first and second phases are spaced 180° apart. The coupled air-core inductors per group of such orientation, separation distance and mutual inductance polarity relative to each other such that magnetic coupling between the two or more inductors at each phase results in a net increase in effective inductance per unit volume. Each air-core inductor is a metal slab of defined length, height and thickness formed using back-end-of-line semiconductor manufacturing process.Type: ApplicationFiled: December 9, 2019Publication date: April 9, 2020Inventors: Xin Zhang, Todd E. Takken, Naigang Wang, Leland Chang
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Patent number: 10540583Abstract: Technical solutions are described to accelerate training of a multi-layer convolutional neural network. According to one aspect, a computer implemented method is described. A convolutional layer includes input maps, convolutional kernels, and output maps. The method includes a forward pass, a backward pass, and an update pass that each include convolution calculations. The described method performs the convolutional operations involved in the forward, the backward, and the update passes based on a first, a second, and a third perforation map respectively. The perforation maps are stochastically generated, and distinct from each other. The method further includes interpolating results of the selective convolution operations to obtain remaining results. The method includes iteratively repeating the forward pass, the backward pass, and the update pass until the convolutional neural network is trained. Other aspects such as a system, apparatus, and computer program product are also described.Type: GrantFiled: November 30, 2015Date of Patent: January 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leland Chang, Suyog Gupta
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Publication number: 20200005125Abstract: A compensated deep neural network (compensated-DNN) is provided. A first vector having a set of components and a second vector having a set of corresponding components are received. A component of the first vector includes a first quantized value and a first compensation instruction, and a corresponding component of the second vector includes a second quantized value and a second compensation instruction. The first quantized value is multiplied with the second quantized value to compute a raw product value. The raw product value is compensated for a quantization error according to the first and second compensation instructions to produce a compensated product value. The compensated product value is added into an accumulated value for the dot product. The accumulated value is converted into an output vector of the dot product. The output vector includes an output quantized value and an output compensation instruction.Type: ApplicationFiled: June 27, 2018Publication date: January 2, 2020Inventors: Swagath Venkataramani, Shubham Jain, Vijayalakshmi Srinivasan, Jungwook Choi, Leland Chang
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Patent number: 10505456Abstract: A multi-phase buck switching converter having grouped pairs of phases, each phase using two magnetically coupled air-core inductors. For each group, a first driver circuit controlling switching of a first power transistor switching circuit coupled to a first air-core inductor output for driving an output load at the first phase. A second driver circuit controlling switching of a second power transistor switching circuit coupled to a second air-core inductor output for driving said output load at the second phase. The first and second phases are spaced 180° apart. The coupled air-core inductors per group of such orientation, separation distance and mutual inductance polarity relative to each other such that magnetic coupling between the two or more inductors at each phase results in a net increase in effective inductance per unit volume. Each air-core inductor is a metal slab of defined length, height and thickness formed using back-end-of-line semiconductor manufacturing process.Type: GrantFiled: September 7, 2018Date of Patent: December 10, 2019Assignee: International Business Machines CorporationInventors: Xin Zhang, Todd E. Takken, Naigang Wang, Leland Chang
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Publication number: 20190288012Abstract: A silicon-on-insulator substrate which includes a semiconductor substrate, a buried oxide layer, and a semiconductor layer is provided. A hard mask layer is formed over a first region of the silicon-on-insulator substrate. A first silicon-germanium layer is epitaxially grown on the semiconductor layer within a second region of the silicon-on-insulator substrate. The second region is at least a portion of the semiconductor layer not covered by the hard mask layer. A thermal annealing process is performed, such that germanium atoms from the first silicon-germanium layer are migrated to the portion of the semiconductor layer to form a second silicon-germanium layer. The hard mask layer is removed. A layer of semiconductor material is epitaxially grown on top of the semiconductor layer and the second silicon-germanium layer, where the layer of semiconductor material composed of the same material as semiconductor layer.Type: ApplicationFiled: June 4, 2019Publication date: September 19, 2019Inventors: Josephine B. Chang, Leland Chang, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 10380479Abstract: Technical solutions are described to accelerate training of a multi-layer convolutional neural network. According to one aspect, a computer implemented method is described. A convolutional layer includes input maps, convolutional kernels, and output maps. The method includes a forward pass, a backward pass, and an update pass that each include convolution calculations. The described method performs the convolutional operations involved in the forward, the backward, and the update passes based on a first, a second, and a third perforation map respectively. The perforation maps are stochastically generated, and distinct from each other. The method further includes interpolating results of the selective convolution operations to obtain remaining results. The method includes iteratively repeating the forward pass, the backward pass, and the update pass until the convolutional neural network is trained. Other aspects such as a system, apparatus, and computer program product are also described.Type: GrantFiled: October 8, 2015Date of Patent: August 13, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leland Chang, Suyog Gupta
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Publication number: 20190228289Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.Type: ApplicationFiled: March 29, 2019Publication date: July 25, 2019Inventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno
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Patent number: 10361219Abstract: A silicon-on-insulator substrate which includes a semiconductor substrate, a buried oxide layer, and a semiconductor layer is provided. A hard mask layer is formed over a first region of the silicon-on-insulator substrate. A first silicon-germanium layer is epitaxially grown on the semiconductor layer within a second region of the silicon-on-insulator substrate. The second region is at least a portion of the semiconductor layer not covered by the hard mask layer. A thermal annealing process is performed, such that germanium atoms from the first silicon-germanium layer are migrated to the portion of the semiconductor layer to form a second silicon-germanium layer. The hard mask layer is removed. A layer of semiconductor material is epitaxially grown on top of the semiconductor layer and the second silicon-germanium layer, where the layer of semiconductor material composed of the same material as semiconductor layer.Type: GrantFiled: June 30, 2015Date of Patent: July 23, 2019Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Leland Chang, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 10331998Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.Type: GrantFiled: December 8, 2015Date of Patent: June 25, 2019Assignee: International Business Machines CorporationInventors: John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha, Robert K. Montoye, Jae-sun Seo, Jose A. Tierno