Abstract: A system comprising: a waveguide assembly comprising a plurality of waveguides, the plurality of waveguides comprising at least a first waveguide and a second waveguide, and an integrated circuit package, IC package, comprising a plurality of launchers to one or more of transmit signalling to and receive signalling from a respective one of the plurality of waveguides, wherein the waveguide assembly comprises a surface configured to be coupled to the IC package and each of the plurality of waveguides comprises an opening in the surface configured to be aligned with its respective launcher, and wherein each of the openings has a major dimension and a minor dimension, wherein the major dimension is larger than the minor dimension, and wherein the major dimension of at least the opening of the first waveguide is oriented perpendicular to the major dimension of the opening of the second waveguide.

Abstract: A packaging assembly and methodology provide a PCB substrate with one or more waveguide apertures and a conductive pattern which includes a plurality of landing pads that are disposed around peripheral edges of each waveguide aperture and that are connected to one another by trace lines so that, upon attachment and reflow of solder balls to the plurality of landing pads, the solder balls reflow along the trace lines to form a fully closed solder waveguide shielding wall disposed around peripheral edges of the first waveguide aperture.

Abstract: A method of forming a semiconductor device is provided. The method includes encapsulating with an encapsulant at least a portion of a semiconductor die and a package substrate, the encapsulant including an additive selectively activated by way of a laser. A first opening is formed in the encapsulant, the first opening exposing a predetermined first portion of the package substrate. The additive is activated at the sidewalls of the first opening. A second opening is formed in the encapsulant, the second opening encircling the first opening and exposing a predetermined second portion of the package substrate. The additive is activated at the sidewalls the second opening. A conductive material is plated on the additive activated portions of the encapsulant.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a non-conductive layer over an active side of a semiconductor die partially encapsulated with an encapsulant. An opening in the non-conductive layer is formed exposing a portion of a bond pad of the semiconductor die. A laser ablated trench is formed at a surface of the non-conductive layer proximate to a perimeter of the opening. A bottom surface of the laser ablated trench is substantially roughened. An under-bump metallization (UBM) structure is formed over the bond pad and laser ablated trench.

Abstract: A packaging assembly and methodology provide a PCB substrate with one or more waveguide apertures and a conductive pattern which includes a plurality of landing pads that are disposed around peripheral edges of each waveguide aperture and that are connected to one another by trace lines so that, upon attachment and reflow of solder balls to the plurality of landing pads, the solder balls reflow along the trace lines to form a fully closed solder waveguide shielding wall disposed around peripheral edges of the first waveguide aperture.

Abstract: A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.

Abstract: A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.

Abstract: A structure is provided that reduces the stress generated in a semiconductor device package during cooling subsequent to solder reflow operations for coupling semiconductor devices to a printed circuit board (PCB). Stress reduction is provided by coupling solder lands to metal-layer structures using traces on the PCB that are oriented approximately perpendicular to lines from an expansion neutral point associated with the package. In many cases, especially where the distribution of solder lands of the semiconductor device package are uniform, the expansion neutral point is in the center of the semiconductor device package. PCB traces having such an orientation experience reduced stress due to thermal-induced expansion and contraction as compared to traces having an orientation along a line to the expansion neutral point.

Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.

Abstract: A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.

Abstract: A structure is provided that reduces the stress generated in a semiconductor device package during cooling subsequent to solder reflow operations for coupling semiconductor devices to a printed circuit board (PCB). Stress reduction is provided by coupling solder lands to metal-layer structures using traces on the PCB that are oriented approximately perpendicular to lines from an expansion neutral point associated with the package. In many cases, especially where the distribution of solder lands of the semiconductor device package are uniform, the expansion neutral point is in the center of the semiconductor device package. PCB traces having such an orientation experience reduced stress due to thermal-induced expansion and contraction as compared to traces having an orientation along a line to the expansion neutral point.

Abstract: One embodiment of a packaged semiconductor device includes: a redistributed layer (RDL) structure formed over an active side of a semiconductor die embedded in mold compound, the RDL structure includes a plurality of solder ball pads that in turn includes: a set of first solder ball pads located on a front side of the packaged semiconductor device within a footprint of the semiconductor die, and a set of second solder ball pads located on the front side of the packaged semiconductor device outside of the footprint of the semiconductor die, each first solder ball pad includes a first center portion having a first diameter measured between opposite outer edges of the first center portion, each second solder ball pad includes a second center portion having a second diameter measured between opposite outer edges of the second center portion, and the first diameter is smaller than the second diameter.

Abstract: An apparatus comprising: a substrate; an integrated circuit region formed in the substrate; a seal ring disposed in the substrate to form a ring around the integrated circuit region, the seal ring configured to provide for protection against one or more of moisture ingress and ion ingress to the integrated circuit region and crack propagation through the substrate; and a defect sensor comprising a conductive track formed of at least one conductive layer in the substrate, the conductive track disposed outwardly of the seal ring and arranged to at least partially surround the integrated circuit region and seal ring, the conductive track having a first end terminal and a second end terminal to receive a detection signal therebetween to pass through the conductive track to detect a break in the conductive track and thereby a defect in the substrate.

Abstract: An integrated circuit package is described comprising an integrated circuit die and an antenna structure coupled to the integrated circuit die and comprising a stacked arrangement of metal and dielectric layers, wherein a first metal layer includes a planar antenna and at least one further metal layer comprises an artificial dielectric layer. The integrated circuit package may improve the directionality of the antenna and reduces the sensitivity of the antenna to the printed circuit board on which the integrated circuit package is mounted.

Abstract: One example discloses a component carrier, including: a cavity; wherein the cavity includes a set of cavity registration features configured to engage with a set of component registration features on a component; and wherein the cavity registration features are within the cavity.

Abstract: An apparatus comprising: a substrate; an integrated circuit region formed in the substrate; a seal ring disposed in the substrate to form a ring around the integrated circuit region, the seal ring configured to provide for protection against one or more of moisture ingress and ion ingress to the integrated circuit region and crack propagation through the substrate; and a defect sensor comprising a conductive track formed of at least one conductive layer in the substrate, the conductive track disposed outwardly of the seal ring and arranged to at least partially surround the integrated circuit region and seal ring, the conductive track having a first end terminal and a second end terminal to receive a detection signal therebetween to pass through the conductive track to detect a break in the conductive track and thereby a defect in the substrate.

Abstract: This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.

Abstract: An integrated circuit package is described comprising an integrated circuit die and an antenna structure coupled to the integrated circuit die and comprising a stacked arrangement of metal and dielectric layers, wherein a first metal layer includes a planar antenna and at least one further metal layer comprises an artificial dielectric layer. The integrated circuit package may improve the directionality of the antenna and reduces the sensitivity of the antenna to the printed circuit board on which the integrated circuit package is mounted.

Abstract: One example discloses a component carrier, including: a cavity; wherein the cavity includes a set of cavity registration features configured to engage with a set of component registration features on a component; and wherein the cavity registration features are within the cavity.

Abstract: This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.