Patents by Inventor Leo van Gemert

Leo van Gemert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE AND METHOD OF MAKING A SEMICONDUCTOR DEVICE
    Publication number: 20170148697
    Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.
    Type: Application
    Filed: November 3, 2016
    Publication date: May 25, 2017
    Inventors: Tonny Kamphuis, Leo van Gemert, Hans van Rijckevorsel, Sascha Moeller, Hartmut Buenning, Steffen Holland, Y Kuang Huang
  • Fan-out chip scale package
    Patent number: 8679963
    Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: March 25, 2014
    Assignee: NXP B.V.
    Inventors: Jan Gulpen, Tonny Kamphuis, Pieter Hochstenbach, Leo Van Gemert, Eric Van Grunsven, Marc De Samber
  • FAN-OUT CHIP SCALE PACKAGE
    Publication number: 20130273731
    Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.
    Type: Application
    Filed: June 12, 2013
    Publication date: October 17, 2013
    Inventors: Jan GULPEN, Tonny KAMPHUIS, Pieter HOCHSTENBACH, Leo VAN GEMERT, Eric Van GRUNSVEN, Marc De SAMBER
  • Fan-out chip scale package
    Patent number: 8482136
    Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: July 9, 2013
    Assignee: NXP B.V.
    Inventors: Jan Gulpen, Tonny Kamphuis, Pieter Hochstenbach, Leo van Gemert, Eric van Grunsven, Marc de Samber
  • FAN-OUT CHIP SCALE PACKAGE
    Publication number: 20110156237
    Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 30, 2011
    Applicant: NXP B.V.
    Inventors: Jan Gulpen, Tonny Kamphuis, Pieter Hochstenbach, Leo van Gemert, Eric van Grunsven, Marc de Samber